Design of Low-jitter, Multi-phase Clock Generation Circuit for Geiger-mode Avalanche Focal Plane Array Applications

Xu LIU; Yunduo LI; Lianhua YE; Zhangcheng HUANG; Yingjie MA; Songlei HUANG; Jiaxiong FANG

doi:10.11999/JEIT210060

Volume 43 Issue 6

Jun. 2021

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Article Navigation > Journal of Electronics & Information Technology > 2021 > 43(6): 1565-1573

Xu LIU, Yunduo LI, Lianhua YE, Zhangcheng HUANG, Yingjie MA, Songlei HUANG, Jiaxiong FANG. Design of Low-jitter, Multi-phase Clock Generation Circuit for Geiger-mode Avalanche Focal Plane Array Applications[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1565-1573. doi: 10.11999/JEIT210060

Citation:

Xu LIU, Yunduo LI, Lianhua YE, Zhangcheng HUANG, Yingjie MA, Songlei HUANG, Jiaxiong FANG. Design of Low-jitter, Multi-phase Clock Generation Circuit for Geiger-mode Avalanche Focal Plane Array Applications[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1565-1573. doi: 10.11999/JEIT210060

Citation:

Xu LIU, Yunduo LI, Lianhua YE, Zhangcheng HUANG, Yingjie MA, Songlei HUANG, Jiaxiong FANG. Design of Low-jitter, Multi-phase Clock Generation Circuit for Geiger-mode Avalanche Focal Plane Array Applications[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1565-1573. doi: 10.11999/JEIT210060

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Design of Low-jitter, Multi-phase Clock Generation Circuit for Geiger-mode Avalanche Focal Plane Array Applications

doi: 10.11999/JEIT210060 cstr: 32379.14.JEIT210060

Xu LIU^{1, 2, 3},
Yunduo LI^{1, 2, 3},
Lianhua YE^{1, 2, 3},
Zhangcheng HUANG^{1, 2},
Yingjie MA^{1, 2},
Songlei HUANG^{1, 2
,
,},
Jiaxiong FANG^{1, 2}

1.
State Key Laboratories of Transducer Technology, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China
2.
Key Laboratory of Infrared Imaging Materials and Detectors, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China
3.
University of Chinese Academy of Sciences, Beijing 100049, China

Funds: The National Natural Science Foundation of China(62075229, 61675225)

Received Date: 2021-01-18
Rev Recd Date: 2021-04-19

Available Online: 2021-04-30

Publish Date: 2021-06-18

Abstract

Abstract

A low-jitter multi-phase clock generation circuit is designed based on a global shared Delay Locked Loop (DLL) and a two-dimensional H-shaped clock tree network for Geiger-mode avalanche focal plane array applications. The DLL adopts an eight-phase voltage-controlled delay chain, a double-edge trigger phase detector and a start reset module. A differential charge pump structure is introduced to reduce the current mismatch between charging and discharging and lower the clock timing jitter. H clock tree structure is involved to diminish the phase variation induced by the asymmetry of the transmission route for large scale integrated circuit, ensuring an equal delay of the multi-channel split-phase clock signal to the pixel unit. The locking frequency range of 150～400 MHz, phase noises below -127 dBc/Hz at 1 MHz offset, RMS timing jitter of below 2.5 ps and static phase error below 65 ps are achieved based on a 0.18 µm digital-analog hybrid CMOS technology.
- Global clock,
- Delay Locked Loop (DLL),
- Differential charge pump,
- H clock tree,
- Geiger avalanche focal plane

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References(16)

References

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