Design of Low-jitter, Multi-phase Clock Generation Circuit for Geiger-mode Avalanche Focal Plane Array Applications

Xu LIU; Yunduo LI; Lianhua YE; Zhangcheng HUANG; Yingjie MA; Songlei HUANG; Jiaxiong FANG

doi:10.11999/JEIT210060

Volume 43 Issue 6

Jun. 2021

Turn off MathJax

Article Contents

Article Navigation > Journal of Electronics & Information Technology > 2021 > 43(6): 1565-1573

Xu LIU, Yunduo LI, Lianhua YE, Zhangcheng HUANG, Yingjie MA, Songlei HUANG, Jiaxiong FANG. Design of Low-jitter, Multi-phase Clock Generation Circuit for Geiger-mode Avalanche Focal Plane Array Applications[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1565-1573. doi: 10.11999/JEIT210060

Citation:

Xu LIU, Yunduo LI, Lianhua YE, Zhangcheng HUANG, Yingjie MA, Songlei HUANG, Jiaxiong FANG. Design of Low-jitter, Multi-phase Clock Generation Circuit for Geiger-mode Avalanche Focal Plane Array Applications[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1565-1573. doi: 10.11999/JEIT210060

Citation:

Xu LIU, Yunduo LI, Lianhua YE, Zhangcheng HUANG, Yingjie MA, Songlei HUANG, Jiaxiong FANG. Design of Low-jitter, Multi-phase Clock Generation Circuit for Geiger-mode Avalanche Focal Plane Array Applications[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1565-1573. doi: 10.11999/JEIT210060

PDF( 4486 KB)

Design of Low-jitter, Multi-phase Clock Generation Circuit for Geiger-mode Avalanche Focal Plane Array Applications

doi: 10.11999/JEIT210060

Xu LIU^{1, 2, 3},
Yunduo LI^{1, 2, 3},
Lianhua YE^{1, 2, 3},
Zhangcheng HUANG^{1, 2},
Yingjie MA^{1, 2},
Songlei HUANG^{1, 2
,
,},
Jiaxiong FANG^{1, 2}

1.
State Key Laboratories of Transducer Technology, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China
2.
Key Laboratory of Infrared Imaging Materials and Detectors, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China
3.
University of Chinese Academy of Sciences, Beijing 100049, China

Funds: The National Natural Science Foundation of China(62075229, 61675225)

Received Date: 2021-01-18
Rev Recd Date: 2021-04-19

Available Online: 2021-04-30

Publish Date: 2021-06-18

Abstract

Abstract

A low-jitter multi-phase clock generation circuit is designed based on a global shared Delay Locked Loop (DLL) and a two-dimensional H-shaped clock tree network for Geiger-mode avalanche focal plane array applications. The DLL adopts an eight-phase voltage-controlled delay chain, a double-edge trigger phase detector and a start reset module. A differential charge pump structure is introduced to reduce the current mismatch between charging and discharging and lower the clock timing jitter. H clock tree structure is involved to diminish the phase variation induced by the asymmetry of the transmission route for large scale integrated circuit, ensuring an equal delay of the multi-channel split-phase clock signal to the pixel unit. The locking frequency range of 150～400 MHz, phase noises below -127 dBc/Hz at 1 MHz offset, RMS timing jitter of below 2.5 ps and static phase error below 65 ps are achieved based on a 0.18 µm digital-analog hybrid CMOS technology.
- Global clock,
- Delay Locked Loop (DLL),
- Differential charge pump,
- H clock tree,
- Geiger avalanche focal plane

FullText(HTML)

References(16)

References

[1]	舒嵘, 黄庚华, 孔伟. 空间激光测高技术发展及展望[J]. 红外与激光工程, 2020, 49(11): 9–18. SHU Rong, HUANG Genghua, and KONG Wei. Development and review of space-based laser altimetry technology[J]. Infrared and Laser Engineering, 2020, 49(11): 9–18.
[2]	陈兆东. 高距离精度条纹探测和单光子计数复合激光三维成像研究[D]. [博士论文], 哈尔滨工业大学, 2019. CHEN Zhaodong. Research on high range accuracy hybrid three dimensional laser imaging based on streak array detecting and single-photon counting[D]. [Ph. D. dissertation], Harbin Institute of Technology, 2019.
[3]	HENDERSON R K, JOHNSTON N, ROCCA F M D, et al. A 192×128 time correlated SPAD image sensor in 40-nm CMOS technology[J]. IEEE Journal of Solid-State Circuits, 2019, 54(7): 1907–1916. doi: 10.1109/JSSC.2019.2905163
[4]	JIANG Xudong, ITZLER M, O’DONNELL K, et al. InP-based single-photon detectors and Geiger-mode APD arrays for quantum communications applications[J]. IEEE Journal of Selected Topics in Quantum Electronics, 2015, 21(3): 3800112.
[5]	DENG Shijie, GORDON D, and MORRISON A P. A Geiger-mode APD photon counting system with adjustable dead-time and interchangeable detector[J]. IEEE Photonics Technology Letters, 2016, 28(1): 99–102. doi: 10.1109/LPT.2015.2487342
[6]	刘俊良, 李永富, 张春芳, 等. 基于APD-PIN结电容平衡电路的门控单光子探测器[J]. 红外与激光工程, 2015, 44(11): 3181–3185. LIU Junliang, LI Yongfu, ZHANG Chunfang, et al. Single-photon detector based on GPQC with balanced APD-PIN junction capacitance[J]. Infrared and Laser Engineering, 2015, 44(11): 3181–3185.
[7]	王燕, 王鹏辉. 激光主动成像技术综述[J]. 电子质量, 2019(7): 1–3. WANG Yan and WANG Penghui. Overview of laser active imaging technology[J]. Electronics Quality, 2019(7): 1–3.
[8]	吴金, 俞向荣, 史书芳, 等. 采用APD单光子阵列读出集成电路的红外测距技术[J]. 红外与激光工程, 2017, 46(6): 69–74. WU Jin, YU Xiangrong, SHI Shufang, et al. Infrared ranging technology by using single photon APD array readout integrated circuit[J]. Infrared and Laser Engineering, 2017, 46(6): 69–74.
[9]	JAHROMI S, JANSSON J P, KERÄNEN P, et al. A 32 × 128 SPAD-257 TDC receiver IC for pulsed TOF solid-State 3-D imaging[J]. IEEE Journal of Solid-State Circuits, 2020, 55(7): 1960–1970. doi: 10.1109/JSSC.2020.2970704
[10]	NICLASS C, SOGA M, MATSUBARA H, et al. A 100-m range 10-frame/s 340 ×96-pixel time-of-flight depth sensor in 0.18-µm CMOS[J]. IEEE Journal of Solid-State Circuits, 2013, 48(2): 559–572. doi: 10.1109/JSSC.2012.2227607
[11]	VERGHESE S, DONNELLY J P, DUERR E K, et al. Arrays of InP-based avalanche photodiodes for photon counting[J]. IEEE Journal of Selected Topics in Quantum Electronics, 2007, 13(4): 870–886. doi: 10.1109/JSTQE.2007.904464
[12]	REZAEIAN A, ARDESHIR G, and GHOLAMI M. A low-power and high-frequency phase frequency detector for a 3.33-GHz delay locked loop[J]. Circuits, Systems, and Signal Processing, 2020, 39(4): 1735–1750. doi: 10.1007/s00034-019-01232-9
[13]	ZHU Shijia, WANG Yu, YE Fan, et al. A clock interpolation structure using DLL for clock distribution in ADC[C]. Proceedings of the 2017 IEEE 12th International Conference on ASIC, Guiyang, China, 2017: 769–772.
[14]	CHITHRA and KRISHNAPURA N. A flexible 18-channel multi-hit time-to-digital converter for trigger-based data acquisition systems[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(6): 1892–1901. doi: 10.1109/TCSI.2020.2969977
[15]	CHITHRA and KRISHNAPURA N. Static phase offset reduction technique for delay locked loops[C]. Proceedings of 2019 IEEE International Symposium on Circuits and Systems, Sapporo, Japan, 2019: 1–5.
[16]	CHENG S, TONG H, SILVA-MARTINEZ J, et al. Design and analysis of an ultrahigh-speed glitch-free fully differential charge pump with minimum output current variation and accurate matching[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2006, 53(9): 843–847. doi: 10.1109/TCSII.2006.879100