A Fast and Efficient FPGA-based Level Set Hardware Accelerator for Image Segmentation

Ye LIU; Jianbiao XIAO; Fei WU; Liang CHANG; Jun ZHOU

doi:10.11999/JEIT210012

Volume 43 Issue 6

Jun. 2021

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Article Navigation > Journal of Electronics & Information Technology > 2021 > 43(6): 1525-1532

Ye LIU, Jianbiao XIAO, Fei WU, Liang CHANG, Jun ZHOU. A Fast and Efficient FPGA-based Level Set Hardware Accelerator for Image Segmentation[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1525-1532. doi: 10.11999/JEIT210012

Citation:

Ye LIU, Jianbiao XIAO, Fei WU, Liang CHANG, Jun ZHOU. A Fast and Efficient FPGA-based Level Set Hardware Accelerator for Image Segmentation[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1525-1532. doi: 10.11999/JEIT210012

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A Fast and Efficient FPGA-based Level Set Hardware Accelerator for Image Segmentation

doi: 10.11999/JEIT210012

University of Electronic Science and Technology of China, Chengdu 611731, China

Funds: NSAF (U2030204)

Received Date: 2021-01-05
Rev Recd Date: 2021-04-16

Available Online: 2021-04-29

Publish Date: 2021-06-18

Abstract

Abstract

The level set algorithm is widely used for image segmentation due to its high accuracy. In addition, compared to the deep learning-based image segmentation methods, the level set algorithm can be implemented without training data, which reduces significantly the labeling efforts. However, the normal level set algorithm is still developed using software, involving complex computation with a large number of pixels and iterations andcausing long processing time and large power consumption. In this work, an FPGA-based level set hardware accelerator is proposed for image segmentation. The proposed hardware accelerator contains four design components: task-level parallel processing, image splitting processing, fully-pipelined processing architecture, and time-multiplexed gradient and divergence processing engine. Based on the experimental results, the proposed hardware accelerator achieves up to 10.7 times acceleration compared to the level set algorithm executing on the CPU, with only 2.2 W power consumption.
- FPGA,
- Hardware accelerator,
- Level set,
- Image segmentation

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References(20)

References

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