Research on Energy Efficiency Probability Model and Architecture of RISCV Cryptographic Processor

Wei LI; Mengni BIE; Tao CHEN; Aiqing WU; Longmei NAN

doi:10.11999/JEIT210004

Volume 43 Issue 6

Jun. 2021

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Article Navigation > Journal of Electronics & Information Technology > 2021 > 43(6): 1541-1549

Wei LI, Mengni BIE, Tao CHEN, Aiqing WU, Longmei NAN. Research on Energy Efficiency Probability Model and Architecture of RISCV Cryptographic Processor[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1541-1549. doi: 10.11999/JEIT210004

Citation:

Wei LI, Mengni BIE, Tao CHEN, Aiqing WU, Longmei NAN. Research on Energy Efficiency Probability Model and Architecture of RISCV Cryptographic Processor[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1541-1549. doi: 10.11999/JEIT210004

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Research on Energy Efficiency Probability Model and Architecture of RISCV Cryptographic Processor

doi: 10.11999/JEIT210004 cstr: 32379.14.JEIT210004

1.
PLA Information Engineering University, Zhengzhou 450000, China
2.
State Key Laboratory of ASIC and System, Fudan University, Shanghai 200433, China

Received Date: 2021-01-04
Rev Recd Date: 2021-04-07

Available Online: 2021-04-16

Publish Date: 2021-06-18

Abstract

Abstract

This paper establishes an energy efficiency probability model for a dedicated cryptographic processor, and guides the design of the cryptographic processor. The design space exploration problem of a processor is designed as the positioning problem of "1" values in the configuration matrix. The probability matrix is introduced to transform the positioning problem into an optimal configuration probability problem. Based on the idea of machine learning, a probability model for the highest energy efficiency of a dedicated cryptographic processor is proposed. Experiments prove that the energy efficiency probability model in this paper outputs the final result after 2300 iterations on average, and the prediction accuracy rate reaches 92.7%. According to the highest energy efficiency probability model, a collection of computing units that meet high energy efficiency requirements can be obtained, and they are integrated into the open source general-purpose 64 bit RISCV processor core named Ariane. A dedicated processor for energy-efficient cryptography is built. The processor is synthesized under the CMOS 55 nm process, and the results show that compared with Ariane, the area of the proposed cryptographic processor increases by 426874 μm², the key delay increases by 0.51 ns, and the sum of the increasing total time area of the cryptographic algorithm is 0.46, the energy efficiency ratio of common cryptographic algorithms is within the range of 1.6～35.16 Mbps/mW.
- Cryptographic processor,
- Machine learning,
- Energy efficiency probability model,
- High energy efficiency

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References(18)

References

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