Efficient Hardware Optimization Strategies for Deep Neural Networks Acceleration Chip

Meng ZHANG; Jingwei ZHANG; Guoqing LI; Ruixia WU; Xiaoyang ZENG

doi:10.11999/JEIT210002

Volume 43 Issue 6

Jun. 2021

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Article Navigation > Journal of Electronics & Information Technology > 2021 > 43(6): 1510-1517

Meng ZHANG, Jingwei ZHANG, Guoqing LI, Ruixia WU, Xiaoyang ZENG. Efficient Hardware Optimization Strategies for Deep Neural Networks Acceleration Chip[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1510-1517. doi: 10.11999/JEIT210002

Citation:

Meng ZHANG, Jingwei ZHANG, Guoqing LI, Ruixia WU, Xiaoyang ZENG. Efficient Hardware Optimization Strategies for Deep Neural Networks Acceleration Chip[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1510-1517. doi: 10.11999/JEIT210002

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Efficient Hardware Optimization Strategies for Deep Neural Networks Acceleration Chip

doi: 10.11999/JEIT210002

1.
National ASIC Engineering Center, School of Electronic Sci. and Eng., Southeast University, Nanjing 210096, China
2.
National ASIC Key Laboratory, Fudan University, Shanghai 200433, China

Funds: The National Key R&D Program of China(2018YFB2202703), Jiangsu Province of Natural Science and Technology(BK20201145)

Received Date: 2021-01-04
Rev Recd Date: 2021-04-21

Available Online: 2021-04-29

Publish Date: 2021-06-18

Abstract

Abstract

Lightweight neural networks deployed on low-power platforms have proven to be effective solutions for Artificial Intelligence (AI) and Internet Of Things (IOT) domains such as Unmanned Aerial Vehicle (UAV) detection and unmanned driving. However, in the case of limited resources, it is very challenging to build Deep Neural Networks (DNN) accelerator with both high precision and low delay. In this paper, a series of efficient hardware optimization strategies are proposed, including stackable shared Processing Engine (PE) to balance the inconsistency of data reuse and memory access patterns in different convolutions; Regulable loop parallelism and channel augmentation are proposed to increase effectively the access bandwidth between accelerator and external memory. It also improve the efficiency of DNN shallow layers computing; Pre-Workflow is applied to improve the overall parallelism of heterogeneous systems. Verified by Xilinx Ultra96 V2 board, the hardware optimization strategies in this paper improve effectively the design of DNN acceleration chips like iSmart3-SkyNet and SkrSkr-SkyNet. The results show that the optimized accelerator processes 78.576 frames per second, and the power consumption of each picture is 0.068 Joules.
- Deep Neural Networks (DNN),
- Object detection,
- Neural network accelerator,
- Low power consumption,
- Hardware optimization

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References(17)

References

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