High-Robust Sub-threshold Standard Cells Using Schmitt Trigger

Yuejun ZHANG; Jinliang HAN; Huihong ZHANG

doi:10.11999/JEIT210001

Volume 43 Issue 6

Jun. 2021

Turn off MathJax

Article Contents

Article Navigation > Journal of Electronics & Information Technology > 2021 > 43(6): 1550-1558

Yuejun ZHANG, Jinliang HAN, Huihong ZHANG. High-Robust Sub-threshold Standard Cells Using Schmitt Trigger[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1550-1558. doi: 10.11999/JEIT210001

Citation:

Yuejun ZHANG, Jinliang HAN, Huihong ZHANG. High-Robust Sub-threshold Standard Cells Using Schmitt Trigger[J]. Journal of Electronics & Information Technology, 2021, 43(6): 1550-1558. doi: 10.11999/JEIT210001

Citation:

PDF( 6338 KB)

High-Robust Sub-threshold Standard Cells Using Schmitt Trigger

doi: 10.11999/JEIT210001

1.
State Key Laboratory of Application Specific Integrated Circuits and Systems, Shanghai 201210, China
2.
Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China

Funds: The National Natural Science Foundation of China (61871244, 61874078), The Open Research Project Fund of the State Key Laboratory of AISC and Systems (2019KF002), The S&T Plan of Ningbo Science and Technology Department (202002N3134), The Ningbo Natural Science Foundation (202003N4107)

Received Date: 2021-01-04
Rev Recd Date: 2021-04-17

Available Online: 2021-04-30

Publish Date: 2021-06-18

Abstract

Abstract

Sub-threshold circuit is an important development direction of low power consumption. With the reduction of power supply voltage, the performance of standard cell circuits provided by foundries is susceptible to noise and process deviations, which has become a bottleneck restricting sub-threshold chips. The high-robust sub-threshold standard cells are proposed in this work. The Schmitt Trigger (ST) and Inverse Narrow Width Effect (INWE) are used to improve the performance, leakage, robust of the logic gates. Then, the INWE minimum width size and finger layout methods are used to increase the switching threshold of the circuit and the drive current of transistor. Finally, the standard cell library is designed and verified with TSMC 65 nm process. The experimental results show that the power of designed standard cells is reduced about 7.2%～15.6%, the noise margin is improved about 11.5%～15.3%, and the average power of ISCAS test circuit is reduced about 15.8%.
- Standard cell,
- Low power,
- Sub-threshold,
- Schmitt Trigger (ST)

FullText(HTML)

References(18)

References

[1]	WANG A and CHANDRAKASAN A. A 180-mV subthreshold FFT processor using a minimum energy design methodology[J]. IEEE Journal of Solid-State Circuits, 2005, 40(1): 310–319. doi: 10.1109/JSSC.2004.837945
[2]	SHI Weiwei, PENG Panfeng, and CHOY C S. A 90nm passive RFID tag’s custom baseband processor for subthreshold operation below 0.3V[J]. Chinese Journal of Electronics, 2017, 26(4): 720–724. doi: 10.1049/cje.2017.04.006
[3]	WEN Liang, NAN Longmei, ZHANG Jing, et al. 65 nm sub-threshold logic standard cell library using quasi-schmitt-trigger design scheme and inverse narrow width effect aware sizing[J]. IET Circuits, Devices & Systems, 2020, 14(3): 303–310. doi: 10.1049/iet-cds.2019.0028
[4]	ZHOU Jun, JAYAPAL S, BUSZE B, et al. A 40 nm dual-width standard cell library for near/sub-threshold operation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2012, 59(11): 2569–2577. doi: 10.1109/TCSI.2012.2190674
[5]	金威. 面向超低功耗的抗PVT波动电路设计技术研究[D]. [博士论文], 上海交通大学, 2017. JIN Wei. Research on ultra-low power PVT tolerant circuits design techniques[D]. [Ph. D. dissertation], Shanghai Jiao Tong University, 2017.
[6]	MORRIS J. A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries[D]. [Ph. D. dissertation], Newcastle University, 2018.
[7]	MIYAMOTO M, OHTA H, KUMAGAI Y, et al. Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics[J]. IEEE Transactions on Electron Devices, 2004, 51(3): 440–443. doi: 10.1109/TED.2003.822877
[8]	ALAM N, ANAND B, and DASGUPTA S. The impact of process-induced mechanical stress in narrow width devices and circuit design issues[C]. 2012 International Symposium on Electronic System Design, Kolkata, India, 2012: 213–215. doi: 10.1109/ISED.2012.42.
[9]	REYNDERS N and DEHAENE W. Variation-resilient building blocks for ultra-low-energy sub-threshold design[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2012, 59(12): 898–902. doi: 10.1109/TCSII.2012.2231022
[10]	LOTZE N and MANOLI Y. A 62mV 0.13μm CMOS standard-cell-based design technique using schmitt-trigger logic[C]. Proceedings of 2011 IEEE International Solid-State Circuits Conference, San Francisco USA, 2011: 340–342. doi: 10.1109/ISSCC.2011.5746345.
[11]	SHARMA P, JAIN P, and DAS B P. An optimal device sizing for a performance-driven and area-efficient subthreshold cell library for IoT applications[J]. Microelectronics Journal, 2019, 92: 104613. doi: 10.1016/j.mejo.2019.104613
[12]	NISHIZAWA S, ISHIHARA T, and ONODERA H. A flexible structure of standard cell and its optimization method for near-threshold voltage operation[C]. The 2012 IEEE 30th International Conference on Computer Design, Montreal, Canada, 2012: 235–240. doi: 10.1109/ICCD.2012.6378646.
[13]	GEMMEKE T, ASHOUEI M, LIU Bo, et al. Cell libraries for robust low-voltage operation in nanometer technologies[J]. Solid-State Electronics, 2013, 84: 132–141. doi: 10.1016/j.sse.2013.02.006
[14]	AYERS J E. Digital Integrated Circuits: Analysis and Design[M]. 2nd ed. Boca Raton: CRC Press, 2010: 256–257.
[15]	HSIAO S F, TSAI M Y, and WEN C S. Low area/power synthesis using hybrid pass transistor/CMOS logic cells in standard cell-based design environment[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2010, 57(1): 21–25. doi: 10.1109/TCSII.2009.2034198
[16]	JUN J, SONG J, and KIM C. A near-threshold voltage oriented digital cell library for high-energy efficiency and optimized performance in 65nm CMOS process[J] IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(5): 1567–1580. doi: 10.1109/TCSI.2017.2758793.
[17]	BORTOLON F T, MOREIRA M T, MORAES F G, et al. Estimation methods for static noise margins in CMOS subthreshold logic circuits[C]. The 30th Symposium on Integrated Circuits and Systems Design, Fortaleza, Brazil, 2017: 90–95. doi: 10.1145/3109984.3109998.
[18]	丁杰. 0.6V 40nm低电压标准单元库设计[D]. [硕士论文], 东南大学, 2016. DING Jie. Design of 40nm standard cell library for 0.6V low voltage[D]. [Master dissertation], Southeast University, 2016.