Coarse Grained Reconfigurable Architecture Loop Mapping Algorithm Based on Memory Partitioning and Path Reuse

ZHANG Xingming; YUAN Kaijian; GAO Yanzhao

doi:10.11999/JEIT170748

Volume 40 Issue 6

May 2018

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ZHANG Xingming, YUAN Kaijian, GAO Yanzhao. Coarse Grained Reconfigurable Architecture Loop Mapping Algorithm Based on Memory Partitioning and Path Reuse[J]. Journal of Electronics & Information Technology, 2018, 40(6): 1520-1524. doi: 10.11999/JEIT170748

Citation:

ZHANG Xingming, YUAN Kaijian, GAO Yanzhao. Coarse Grained Reconfigurable Architecture Loop Mapping Algorithm Based on Memory Partitioning and Path Reuse[J]. Journal of Electronics & Information Technology, 2018, 40(6): 1520-1524. doi: 10.11999/JEIT170748

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Coarse Grained Reconfigurable Architecture Loop Mapping Algorithm Based on Memory Partitioning and Path Reuse

doi: 10.11999/JEIT170748

Funds:

The National Science Technology Major Project (2016ZX01012101), The National Natural Science Foundation of China (61572520, 61521003)

Received Date: 2017-07-21
Rev Recd Date: 2017-12-18
Publish Date: 2018-06-19

Abstract

Abstract

The current research on Coarse Grained Reconfigurable Architecture (CGRA) loop mapping mainly focuses on operation placement and data routing, but seldom involves data mapping. To solve this problem, a mapping flow based on memory partitioning and path reuse is designed. Firstly, fine grained memory partitioning is used to find the data placement improving the parallelism of data access. Secondly, placement and routing is searched by modulo scheduling. Finally, the routing overhead model is used to balance memory routing and processing unit routing and path reuse strategy is introduced to optimize routing resources. Experimental results validate the performance of proposed approach in initiation interval, instruction per cycle and execution delay.
- Coarse Grained Reconfigurable Architecture (CGRA),
- Loop mapping,
- Memory partitioning,
- Path reuse

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References(13)

References

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