Efficient Encoding Architecture for LDPC Code Based on DVB-S2 Standard

LAN Yazhu; YANG Haigang; LIN Yu

doi:10.11999/JEIT151198

Volume 38 Issue 7

Jul. 2016

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Article Navigation > Journal of Electronics & Information Technology > 2016 > 38(7): 1781-1787

LAN Yazhu, YANG Haigang, LIN Yu. Efficient Encoding Architecture for LDPC Code Based on DVB-S2 Standard[J]. Journal of Electronics & Information Technology, 2016, 38(7): 1781-1787. doi: 10.11999/JEIT151198

Citation:

LAN Yazhu, YANG Haigang, LIN Yu. Efficient Encoding Architecture for LDPC Code Based on DVB-S2 Standard[J]. Journal of Electronics & Information Technology, 2016, 38(7): 1781-1787. doi: 10.11999/JEIT151198

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Efficient Encoding Architecture for LDPC Code Based on DVB-S2 Standard

doi: 10.11999/JEIT151198 cstr: 32379.14.JEIT151198

1.
2.
(System of Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)

Funds:

The National Natural Science Foundation of China (61404140, 61271149, 61106033)

Received Date: 2015-10-29
Rev Recd Date: 2016-03-15
Publish Date: 2016-07-19

Abstract

Abstract

For DVB-S2 standard LDPC code, to achieve an efficient encoding architecture based on FPGA, a fast pipeline parallel and recursive encoding algorithm is proposed which can significantly improve encoding speed and improve the encoding data rate of information throughput. At the same time, the parallel shift operation and parallel XOR processing structure is introduced to calculate code intermediate variable. It can effectively improve the encoding parallel degree and reduce the occupancy volume of storage resources. In addition, according to dynamic adaptive encoding, the storage structure and effective reuse of data storage unit and the RAM address generator are optimized. In this case, the utilization of FPGA resources is further improved. The experiment based on Stratix IV series FPGA for DVB-S2 standard LDPC code, shows that the proposed method can achieve system clock frequency of 126.17 MHz and encoding data rate of information throughput of more than 20 Gbps.
- LDPC code,
- Encoding architecture,
- DVB-S2 standard,
- FPGA

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References(22)

References

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