Abstract: The problem of the hardware realization of a special operation - the square operation is often encountered in the design of digital ASICs, especially the ASICs used in communication and signal processing area. From the study of the regular multiplier designed in VLSI circuit, a realization method for the square operation suitable for VLSI implementation is proposed in this paper. By means of simplifying the part products of the multiplication, big cuts have been made in the circuit scale of the new design.