时序电路的冗余状态变换确认研究
STATE TRANSITION REDUNDANCE IDENTIFICATION
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摘要: 本文以状态跳变图为基础,深入分析冗余变换与非法变换的特征,提出结构冗余和功能冗余的概念,并讨论了可测、不可测故障与冗余之间的联系。最后结合验证和测试生成,提出状态冗余的隐含遍历确认策略。
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关键词:
- 测试生成; 验证; 有限状态机
Abstract: The BDD (Binary Decision Diagram) is very important for representing synchronous circuits. After analyzing and reducing the BDD, the state traversing is proposed on the basis of collapsing of input, routes and states on STG. Finally, the verification for the non-reset circuits has been described. -
Cho H, Hachteland G D. Fast sequential ATPG based on implicit state enumeration. ITC91 1991, 67-74.[2]Calazans N. Advanced ordered and manipulation tecniques for BDD. DA92, 1992, 452-457. -
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