Zhu Dazhong. DESIGN AND RESEARCH OF QUASI-PLANAR SELF-ALIGNED SILICON AVALANCHE ELECTRON EMISSION ARRAY[J]. Journal of Electronics & Information Technology, 1998, 20(3): 429-432.
Citation:
Zhu Dazhong. DESIGN AND RESEARCH OF QUASI-PLANAR SELF-ALIGNED SILICON AVALANCHE ELECTRON EMISSION ARRAY[J]. Journal of Electronics & Information Technology, 1998, 20(3): 429-432.
Zhu Dazhong. DESIGN AND RESEARCH OF QUASI-PLANAR SELF-ALIGNED SILICON AVALANCHE ELECTRON EMISSION ARRAY[J]. Journal of Electronics & Information Technology, 1998, 20(3): 429-432.
Citation:
Zhu Dazhong. DESIGN AND RESEARCH OF QUASI-PLANAR SELF-ALIGNED SILICON AVALANCHE ELECTRON EMISSION ARRAY[J]. Journal of Electronics & Information Technology, 1998, 20(3): 429-432.
The device structure and technical processings of quasi-planar self-aligned silicon avalanche electron emission array are introduced. The processing step at the edge of electron emission region is about 100 nm only and the width of self-aligned current channel of shallow As implantation is about 3 m. Its I-V characteristics show a larger linear region and lower series resistance than that of the previous silicon avalanche electron emission devices. Some of the electron emission characteristics are also discussed in the paper.
黄庆安.真空微电子学的研究与进展.电子学报,1995, 23(10): 134-138.[2]Yicheng Lu, Minjng Wang, Bogoljub Lalevic. IEEE Trans. on ED, 1994, ED-41(3): 439-444.[3]Wang M, Lu Y, Lalevic B. J. Vac. Sci. Technol, 1993, B-11(2): 426-428[4]Meijuan Guo. Proc. 4th Int. Con. on Solid-State and Integrated Circuit Technology.北京:电子工业出版社,1995,485-487.[5]S M Sze. VLSI Technology. 2nd Ed, McGraw-Mill, 1988, ch.3: 111-113.
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