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Volume 28 Issue 4
Aug.  2010
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Yuan Dan-shou, Rong Meng-tian. Reconfigurable and Fast Finite Field Multiplier Architecture[J]. Journal of Electronics & Information Technology, 2006, 28(4): 717-720.
Citation: Yuan Dan-shou, Rong Meng-tian. Reconfigurable and Fast Finite Field Multiplier Architecture[J]. Journal of Electronics & Information Technology, 2006, 28(4): 717-720.

Reconfigurable and Fast Finite Field Multiplier Architecture

  • Received Date: 2004-06-03
  • Rev Recd Date: 2004-09-09
  • Publish Date: 2006-04-19
  • A reconfigurable and fast architecture over Galois field GF (2m )(1<mM) is presented based on the improved serial multiplier. The value m, of the irreducible polynomial degree, can changed by adding a set of configuring signals and logic circuits, which results in that the multiplier architecture is reconfigurable and programmable without changing the hardware. The proposed multiplier architecture has high order of flexibility and low hardware complexity. Compared with the traditional serial multiplier, it can obtain twice speed-up. It suits high-security cryptographic applications with variable finite fields and low complexity requirements.
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