Zhou Ping, Yu Sile. THE DESIGN AND IMPLEMENTATION OF AN FPGA-BASED DIGITAL HDTV VIDEO DECODER[J]. Journal of Electronics & Information Technology, 1998, 20(6): 799-805.
Citation:
Zhou Ping, Yu Sile. THE DESIGN AND IMPLEMENTATION OF AN FPGA-BASED DIGITAL HDTV VIDEO DECODER[J]. Journal of Electronics & Information Technology, 1998, 20(6): 799-805.
Zhou Ping, Yu Sile. THE DESIGN AND IMPLEMENTATION OF AN FPGA-BASED DIGITAL HDTV VIDEO DECODER[J]. Journal of Electronics & Information Technology, 1998, 20(6): 799-805.
Citation:
Zhou Ping, Yu Sile. THE DESIGN AND IMPLEMENTATION OF AN FPGA-BASED DIGITAL HDTV VIDEO DECODER[J]. Journal of Electronics & Information Technology, 1998, 20(6): 799-805.
This paper presents the scheme and its implementation of a video decoder, which can complete real-time decoding the MPEG-2 based coded bit stream. This scheme adopts the parallel processing technique, the operation in pipe line and a large quantity of FPGA. The approach for the motion compensation crossing the border, which is caused by parallel processing, is studied. The architecture of the decoder, the formation of main circuits and the realization of decoding procedue are described.
ISO/IEC IS 13818. Generic Coding of Moving Picture and Associated Audio. Nov. 1994.[2]周萍.数字高清晰度电视视频解码器的研究:[博士论文],天津:天津大学,1996年6月.[3]Xilinx. Inc. The Programmable Logic Data Book. 1994.[4]Grand Alliance HDTV System Specification. Version 1.0. Apr. 1994.[5]Lei S M, Sun M T. An entropy coding system for digital HDTV application. IEEE Trans. on CAS VT, 1991, 1(1): 147-155.
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