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Volume 26 Issue 1
Jan.  2004
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Xiang Dong, Liu Xin, Xu Yi. Partial Scan Design Based on Circuit State Information and Conflict Analysis[J]. Journal of Electronics & Information Technology, 2004, 26(1): 124-130.
Citation: Xiang Dong, Liu Xin, Xu Yi. Partial Scan Design Based on Circuit State Information and Conflict Analysis[J]. Journal of Electronics & Information Technology, 2004, 26(1): 124-130.

Partial Scan Design Based on Circuit State Information and Conflict Analysis

  • Received Date: 2002-08-14
  • Rev Recd Date: 2002-12-31
  • Publish Date: 2004-01-19
  • A multiple phase partial scan design method that breaks critical cycles using a combination of valid circuit state information and conflict analysis is proposed. It is quite cost-effective to obtain circuit state information via logic simulation, therefore, circuit state information is iteratively updated after a given number of partial scan flip-fiops being selected. When all critical cycles in the circuit are broken, our method turns to the con-flict resolution process using an intensive conflict-analysis-based testability measure conflict rather than reducing the sequential depth. The proposed method tries to eliminate the con-flicts and uses a conflict-analysis-based testability measure conflict. Sufficient experimental results are presented to validate the method.
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  • Corno F, Prinetto P, Sonza Reorda M, Violante M. Exploiting symbolic techniques for partial scan flip-flop selection. Proc. of IEEE Design Automation and Test in Europe, Paris, France,Feb. 23-26, 1998: 670-677.[2]Cheng K T, Agrawal V D. A partial scan method for sequential circuits with feedback[J].IEEE Trans. on Computers.1990, 39(4):544-548[3]Chickermane V, Patel J H. An optimization based approach to the partial scan design problem.Proc. of IEEE Int. Test Conf., Washington, DC, Sep. 10-14, 1990: 377-386.[4]Gupta R, Gupta R, Breuer M A. The BALLAST methodology for structured partial scan design[J].IEEE Trans. on Computers.1990, 39(4):538-544[5]Parihk P S, Abramovici M. Testability-based partial scan analysis[J].J. of Electronic Testing.1995,7:61-70[6]Sharma S, Hsiao M. Combination of structural and state analysis for partial scan. Proc. of Int.VLSI Design Conf., Bangalore, India, Jan. 3-7, 2001: 134-139.[7]Saund G S, Hsiao M S, Patel J H. Partial scan beyond cycle cutting. Proc. of IEEE Int. Symp.on Fault-Tolerant Computing, Seattle, Washington, USA, Jun. 24-27, 1997: 320-328.[8]Xiang D, Venkataraman S, Fuchs W K, Patel J H. Partial scan design based on circuit statc information. Proc. of ACM/IEEE Design Automation Conference, Las Vegas, USA, .Junc 1996:807-812.[9]Xiang D, Xu Y, Fujiwara H. Non-scan design for testability for synchronous sequential circuits based on conflict resolution. Accepted to appear in IEEE Trans. on Computers.[10]Xiang D, Fujiwara H. Handling the pin overhead problem of DFTs for high quality and at-speed tests[J].IEEE Trans. on Computer-Aided Design of ICAS.2002, 21(9):1105-1113[11]Kalla P, Ciesielski M J. A comprehensive approach to the partial scan problem using implicit state enumeration[J].IEEE Trans. on Computer-Aided Design of ICAS.2002, 21(7):810-826[12]Niermann T M, Patel J H. HITEC: A test generation package for sequential circuits. Proc. of European Conf. Design Automation, Amsterdam, The Netherlands, Feb. 25-28, 1991: 214-218.
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