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Volume 28 Issue 9
Sep.  2010
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Ji Ai-ming, Shen Hai-bin, Yan Xiao-lang. A Fast Method for Reconfigurable Architecture Design Space Exploration[J]. Journal of Electronics & Information Technology, 2006, 28(9): 1744-1747.
Citation: Ji Ai-ming, Shen Hai-bin, Yan Xiao-lang. A Fast Method for Reconfigurable Architecture Design Space Exploration[J]. Journal of Electronics & Information Technology, 2006, 28(9): 1744-1747.

A Fast Method for Reconfigurable Architecture Design Space Exploration

  • Received Date: 2004-12-31
  • Rev Recd Date: 2005-08-08
  • Publish Date: 2006-09-19
  • Based on evaluation model, approach to estimating ATP(Area Timing and Power) of RA(Reconfigurable Architecture) at algorithm level is studied. According to ATP, RA design space exploration is carried out in two stages. First,the lowest cost for each architecture to implement all algorithms is searched; second, the optimized architecture is explored in RA design space. This method is independent on any architecture. It can value RA roundly, and fast produce a global optimal result. Application example has shown that it is effectively to guide RA design at an early stage.
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  • Rose J A, El Gamal A, Sangiovannt-Vincenteli A. Architecture of field programmable gate arrays[J].Proc. IEEE.1993, 81(7):1013-1029[2]Hartenstein R, Hofmann T H, Nageldinger U. Design-space exploration of low power coarse grained reconfigurable datapath array architectures. Proc. of Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop. Gottingen, Germany, 2000: 118-128.[3]Hartenstein R. A decade of reconfigurable computing: a visionary retrospective. Proceedings of Conference on Design, Automation and Test in Europe. Munich, Germany, 2001: 642- 649.[4]Hartenstein R , Herz M , Hofmann T, et al.. KressArray Xplorer:a new CAD environment to optimize reconfigurable datapath array architectures. Proceedings of the ASP-DAC 2000, Yokohama , Japan, 2000: 163-168.[5]Betz V, Rose J, Marquart A. Architecture and CAD for Deep Submicron FPGAs. Dordrecht: Kluwer Academic Publishers, 1999: 50-61.[6]Bossuet L, Gogniat G, Philippe J L. Fast design spaceexploration method for reconfigurable architectures. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, CSREA, 2003.[7]Darnauer J, Dai W W. A method for generation random circuits and its application to routability measurement. Proc of International Conference on Symp. Field Programmable Gate Arrays, 1996: 66-72.[8]Davis J A, De V K, Meundl J D. A stochastic wire-length distribution for GigaScale Integration (GSI)Part I: Derivation and validation[J].IEEE Trans. on Electron Devices.1998, 45(3):580-589[9]Kahng A B, Mantik S, Stroobandt D. Toward accurate models of achievable routing[J].IEEE Trans. on Computer Aided Design of Intergrated Circuits and System.2001, 20(5):648-658[10]Bossuet L .[J].Wayne B , Guy G, et al.. Targeting tiled architectures in design exploration. Proc of the International Parallel and Distributed Processing Symposium (IPDPS03). Austin : IEEE Computer Society.2003,:-[11]Landman P. High-level power estimation. Low Power Electronics and Design, 1996., International Symposium on Monterey CA, 1996:29-35.
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