Zhang Bo, Zhang Huan-chun, Jing Ya-zhi. A Hardware Realization of Order Morphological Image Processor[J]. Journal of Electronics & Information Technology, 2004, 26(12): 1856-1862.
Citation:
Zhang Bo, Zhang Huan-chun, Jing Ya-zhi. A Hardware Realization of Order Morphological Image Processor[J]. Journal of Electronics & Information Technology, 2004, 26(12): 1856-1862.
Zhang Bo, Zhang Huan-chun, Jing Ya-zhi. A Hardware Realization of Order Morphological Image Processor[J]. Journal of Electronics & Information Technology, 2004, 26(12): 1856-1862.
Citation:
Zhang Bo, Zhang Huan-chun, Jing Ya-zhi. A Hardware Realization of Order Morphological Image Processor[J]. Journal of Electronics & Information Technology, 2004, 26(12): 1856-1862.
Firstly, order morphological transformations on gray image are introduced in this paper, then an image processing system in which order morphological transformation is implemented by hardware is presented. The system is composed of Digital Signal Pro-cessor (DSP) and Field Programmable Gate Array (FPGA), one FPGA as coprocessor can implement different functions due to its re-configurable characteristic. The images processed by software and hardware realization are compared in effect and speed. The algorithm is implemented successfully and its speed is very high. It makes possible that mathematical morphology is applicable in real time image processing.
Serra J. Image Analysis and Mathematical Morphology. New York, Academic Press, 1982: 5-26.[2]Arce G R, Foster R E. Detail preserving ranked-order based filters for image processing. IEEE Trans. on ASSP, 1989, ASSP-37(1): 83-98.[3]吴敏金.二值序列的复合顺序滤波.电子学报,1986,14(3):76-81.[4]吴敏金.图象形态学.上海:上海科学技术文献出版社,1991:214-247.[5]苏涛,吴顺君,廖晓群.高性能数字信号处理器与高速实时信号处理.西安:西安电子科技大学出版社,1999:46-60.[6]曾涛,李眈,龙腾.高速实时数字信号处理器SHARC的原理及其应用.北京:北京理工大学出版社,2000:73-100.[7]Xilinx Inc. Virtex-Ⅱ Platform FPGA Handbook. San Jose, California, Xilinx Inc., 2001: 330-335.Xilinx Inc. Spartan-Ⅱ 2.5V FPGA Family: Functional Description. San Jose, California, Xilinx Inc., 2001: 7-20.
DownLoad: