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Volume 26 Issue 4
Apr.  2004
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LUO Zhiyong, ZHU Zihao, YOU Bo, LIU Jiahui. Virtual Workflow Constrained Time-accuracy Optimization Algorithm Scheduling by Iterative Reduction[J]. Journal of Electronics & Information Technology, 2018, 40(8): 2013-2019. doi: 10.11999/JEIT171038
Citation: Sun Xiu-bin, Chen Guang-ju, Xie Yong-le. Test Point Selection for Analog Integrated Circuit[J]. Journal of Electronics & Information Technology, 2004, 26(4): 645-650.

Test Point Selection for Analog Integrated Circuit

  • Received Date: 2002-11-15
  • Rev Recd Date: 2003-03-24
  • Publish Date: 2004-04-19
  • How to select an optimum set of test points or test vectors has become very critical to analog integrated circuit fault diagnosis. A test point selection method based on testability measure is presented in this paper. Using Determinant Decision Diagrams (DDDs), symbolic transfer functions of circuit under test are constructed and its testability measure can be calculated exactly and efficiently. This method eliminates completely the unavoidable round-off errors introduced by numerical algorithms and can handle moderate or large integrated circuits.
  • Fedi G, Luchetta A, Manetti S, Piccirilli M C. A new symbolic method for analog circuit testability evaluation[J].IEEE Trans. on Instrumentation and Measurement.1998, 47(2):554-565[2]Berkowitz R S. Conditions for network-element-value solvability. IEEE Trans. on Circuit Theory,1962, CT-9(1): 24-29.[3]Sakes R. A measure of testability and its application to test point selection theory. in Proc. of the 20th Midwest Symposium on Circuits and Systems, Lubbock, Texas Tech. Univ., 1977: 576-583.[4]Liberatore A, Manetti S, Piccirilli M C. A new efficient method for analog circuit testability measurement. in Proc. of Instrumentation and Measurement Technology Conference, Hamamatsu,Japan, 1994: 193-196.[5]Tao Pi, C. -J. Richard Shi. Analog testability analysis by determinant-decision-diagrams based symbolic analysis. in Proc. of the ASP-DAC 2000, Yokohama, Japan, 2000: 541-546.[6]Manthe A, C. -J. Richard Shi. Lower bound based DDD minimization for efficient symbolic circuit analysis. in Proc. of 2001 IEEE International Conference on Computer Design, Los Alamitos,California, 2001: 374-379.[7]Xiangdong Tan, C. -J. Richard Shi. Hierarchical symbolic analysts of large analog circuits with determinant decision diagrams. in Proc. of the 1998 IEEE International Symposium on Circuits and Systems, Monterey, CA, 1998: 318-321.
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