Sun Xiu-bin, Chen Guang-ju, Xie Yong-le. Test Point Selection for Analog Integrated Circuit[J]. Journal of Electronics & Information Technology, 2004, 26(4): 645-650.
Citation:
Sun Xiu-bin, Chen Guang-ju, Xie Yong-le. Test Point Selection for Analog Integrated Circuit[J]. Journal of Electronics & Information Technology, 2004, 26(4): 645-650.
Sun Xiu-bin, Chen Guang-ju, Xie Yong-le. Test Point Selection for Analog Integrated Circuit[J]. Journal of Electronics & Information Technology, 2004, 26(4): 645-650.
Citation:
Sun Xiu-bin, Chen Guang-ju, Xie Yong-le. Test Point Selection for Analog Integrated Circuit[J]. Journal of Electronics & Information Technology, 2004, 26(4): 645-650.
How to select an optimum set of test points or test vectors has become very critical to analog integrated circuit fault diagnosis. A test point selection method based on testability measure is presented in this paper. Using Determinant Decision Diagrams (DDDs), symbolic transfer functions of circuit under test are constructed and its testability measure can be calculated exactly and efficiently. This method eliminates completely the unavoidable round-off errors introduced by numerical algorithms and can handle moderate or large integrated circuits.
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