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Volume 26 Issue 12
Dec.  2004
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Lu Jian-feng, Wang Shuo-zhong. FPGA Watermarking Based on Modification of Time Constraints[J]. Journal of Electronics & Information Technology, 2004, 26(12): 1882-1887.
Citation: Lu Jian-feng, Wang Shuo-zhong. FPGA Watermarking Based on Modification of Time Constraints[J]. Journal of Electronics & Information Technology, 2004, 26(12): 1882-1887.

FPGA Watermarking Based on Modification of Time Constraints

  • Received Date: 2003-06-28
  • Rev Recd Date: 2003-10-20
  • Publish Date: 2004-12-19
  • Based on modification of time constraints in the FPGA design, a watermark-embedding scheme is proposed for protection of intellectual property rights of the system designer. A coded binary watermark sequence is used to replace the least significant digits of the time constraints in some non-critical paths. The modified time constraints lead to substantial and unique changes in the generated bit stream without altering the performance of the design, both in terms of space and time overheads and the system functionality. The embedded data can be extracted in a reverse procedure. The paper provides a scheme with zero area and low timing overheads, and a significant increase in embedding capacity in comparison with some existing techniques.
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  • Petitcolas F A P, Anderson R J, Kuhn M G. Information hiding - A survey[J].Proc. IEEE.1999,87(7):1062-1078[2]Hartung F, Kutter M. Multimedia watermarking techniques[J].Proc. IEEE.1999, 87(7):1079-1107[3]Lach J, Mangione-Smith W H, Potkonjak M. Signature hiding techniques for FPGA intellectual property protection. International Conference on Computer-Aided Design, San Jose, CA, USA,1998: 186-189.[4]Kahng A B, et al.. Watermarking techniques for intellectual property protection. Design Automation Conference, San Francico, California, USA, 1998: 776-781.Lach J, Mangione-Smith W H, Potkonjak M. Fingerprinting digital circuits on programmable hardware. International Workshop on Information Hiding, Portland, Oregon, USA, 1998: 16-31.[5]Lach J, Mangione-Smith W H, Potkonjak M. Fingerprinting techniques for field programmable gate array intellectual property protection[J].IEEE Trans. on Computer-Aided Design.2001,20(10):1253-1261[6]Lach J, Mangione-Smith W H, Potkonjak M. Robust FPGA intellectual property protection through multiple small watermarks. Design Automation Conference, New Orleans, LA, USA,1999: 831-836.[7]Lach J, Mangione-Smith W H, Potkonjak M. Enhanced intellectual property protection for digital circuits on programmable hardware, International Workshop on Information Hiding, Dresden,Germany, 1999: 286-301.[8]Kahng A B, et al.. Constraint-based watermarking techniques for design IP protection[J].IEEE Trans. on Computer-Aided Design.2001, 20(10):1236-1252[9]Jain A K, Yuan Lin, Pari P R, Qu G. Zero overhead watermarking technique for FPGA designs.GLSVLSI, Washington, DC, USA, 2003: 147-152.[10]Lach J, Mangione-Smith W H, Potkonjak M. FPGA fingerprinting techniques for protecting intellectual property. Custom Integrated Circuits Conference, Santa Clara, CA, USA, 1998: 299-302.[11]Qu G, Potkonjak M. Fingerprinting intellectual property using constraint-addition. Proceedings of the 2000 International Symposium on Low Power Electronics and Design, Rapallo/Portofino Coast, Italy, 2000: 587-592.[12]Schouten R. A whitepaper on SRAM FPGA security. February 2003, http:∥www.fpga.com.cn/advance/skill/SRAM_Security_whitepaper.pdf.
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