A new kind of interconnect crosstalk model and estimation formula for high-speed integrated circuits

Zhao Jun; Liu Lingzhi; Rong Mengtian; Mao Junfa

Volume 25 Issue 4

Apr. 2003

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Article Navigation > Journal of Electronics & Information Technology > 2003 > 25(4): 543-550

Zhao Jun, Liu Lingzhi, Rong Mengtian, Mao Junfa . A new kind of interconnect crosstalk model and estimation formula for high-speed integrated circuits[J]. Journal of Electronics & Information Technology, 2003, 25(4): 543-550.

Citation:

Zhao Jun, Liu Lingzhi, Rong Mengtian, Mao Junfa . A new kind of interconnect crosstalk model and estimation formula for high-speed integrated circuits[J]. Journal of Electronics & Information Technology, 2003, 25(4): 543-550.

Citation:

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A new kind of interconnect crosstalk model and estimation formula for high-speed integrated circuits

Received Date: 2002-01-10
Rev Recd Date: 2002-06-20
Publish Date: 2003-04-19

Abstract

Abstract

In this paper, an interconnect delay estimation model is built up, including the effect of distributed resistance, capacitance and even inductance. Then, on the basis of this model, the respondence of the terminal on the worst condition is analyzed and three-order precise formula to estimate the crosstalk respondence is presented. In the end, a new estimation formula for interconnect crosstalk respondence is derived. Moreover, experimental result is excellent enough to the simulation result of SPICE for practical circuit.

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References(1)

References

Y. Eo, W. R. Eisenstadt, J. Y. Jeong, O. Kwon, A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design, IEEE Trans. on Electron Devices, 2000,47(1), 129-140.[2]T. Sakurai, Closed-form expressions for interconnection delay, coupling and crosstalk in VLSIs,IEEE Trans. on Electron Devices, 1993, 40(1), 118-124.[3]J. Cong , Z. Pan, Interconnect delay estimation models for synthesis and design planning, in Proc. Asia and South Pacific Design Automation Conf., Jan. 1999, 97-100.[4]Y.I. Ismail, E. G. Friedman, J. L. Neves, Figures of merit to characterized the important of on-chip inductance, IEEE Trans. on VLSI Syst. 1999, 7(4), 442-449.[5]Semiconductor Industry Association, National Technology Roadmap for Semiconductor, USA,1997.

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