Study on the degradation induced by acceptor interface state for deep-sub-micron grooved-bate PMOSFET\s

C. Hu, Simulating hot-carrier effects on circuit performance, Semiconductor Science Technology,1992, 7(3), B555-B558.[2]J.E. Chung, M. Jeng, J. E. Moon, P. K. Ku, C. Hu, Low-voltage hot-electron currents and degradation in deep-sub-micrometer MOSFETs, IEEE Trans. on Electron Devices, 1990, 37(7),1651-1657.[3]C. Fiegna, H. Iwai, T. Wada, et al., Scaling the MOS transistor below 0.1 m: Methodology,device structures, and technology requirements, IEEE Trans. on Electron Devices, 1994, 41(6),941-949.[4]C. Hu, S. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, K. W. Terrill, Hot-electron-induced MOSFET degradation-model, monitor and improvement, IEEE Trans. on Electron Devices, 1985, 32(2),375-385.[5]H.I. Kimura, J. Tanaka, H. Noda, Short-channel-effect-suppressed sub-0.1-m grooved-gate MOSFETs with W gate, IEEE Trans. on Electron Devices, 1995, 42(1), 94-99.[6]Paul-Henri Bricout, Emmanuel Dubois, Short-channel effect immunity and current capability of sub-0.1-micron MOSFETs using a recessed channel, IEEE Trans. on Electron Devices, 1996,43(8), 1251-1255.[7]R. Woltjer, G. M. Paulzen, H. G. Pomp, H. Lifka, P. H. Woerlee, Three hot-carrier degradation mechanisms in deep-submicron PMOSFETs, IEEE Trans. on Electron Devices, 1995, 42(1),109-114.[8]Technology Modeling Associates, Inc. Medici Two-Dimensional Device Simulation Program Version 2.3 Users Manual, Vol.1, Feb 1997Technology Modeling Associates, Inc. TSUPREM-4 Two-Dimensional Process Simulation Program Version 6.5 User Manual , May 1997[9]S. Tam, P. Ko, C. Hu, Luck-electron model of channel hot-electron injection in MOSFETs, IEEE Trans. on Electron Devices, 31(9), 1984, 1116-1125.[10]任红霞,郝跃,许冬岗,槽栅NMOSFET抗热载流子效应的研究,物理学报,2000,49(7),741-748.