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Volume 16 Issue 4
Jul.  1994
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Yu Shan, Zhang Dingkang, Huang Chang. 0.8m LDD CMOS RELIABILITY EXPERIMENTS AND ANALYSIS[J]. Journal of Electronics & Information Technology, 1994, 16(4): 402-406.
Citation: Yu Shan, Zhang Dingkang, Huang Chang. 0.8m LDD CMOS RELIABILITY EXPERIMENTS AND ANALYSIS[J]. Journal of Electronics & Information Technology, 1994, 16(4): 402-406.

0.8m LDD CMOS RELIABILITY EXPERIMENTS AND ANALYSIS

  • Received Date: 1993-04-20
  • Rev Recd Date: 1994-01-06
  • Publish Date: 1994-07-19
  • The numerical simulation of two dimensional device is conducted to describe the mechanism of the special substrate current and degradation of submi-cron LDD structure observed in experiments, and finally, the optimum processes for submicron LDD CMOS are proposed.
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  • Ogura S, Tsang P J, Walker W W, et al. IEEE Trans. on ED, 1980, ED-27(8): 1359-1367.[2]Hui J, Hsu F-C, Moll J. IEEE Electron Device Lett. 1985, 6(3): I35-138.[3]Hsu F-C, Chiu K Y. IEEE Electron Device Lett. 984, 5(5): 162-165.[4]杜敏, 黄敞.半导休学报,1988,9(1):1-6.[5]Andhare P N, Nahar R K, Devashrayee N M, et al. Microelectronics Rehab 1990, 30(4):681-690.[6]Koyanagi M, Lewis A G, Martin R A, et al. IEEE Trans. on ED, 1987, ED-34(4): 839-844.[7]余山,章定康,黄敞.半导体学报,1992,13(7): 423-429.[8][8][9]Yu Shan, Zhang Dingkang, Huang Chang. Development of 0.50m CMOS Integrated Circuits Technology, Proc. of 3rd ICSICT. Beijing: 1992, 143-146.[10]余山,章定康,黄敞.高速1m LDD CMOS自对准硅化钛总线交换逻辑集成电路的研制.全国首届专用集成电路(ASIC)学术会议论文集.无锡:1990,203-204.
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