An Improved High-speed Lottery Bus Arbiter

With the development of semiconductor technology, integration of an increasing number of IP (Intellectual Properties) cores into a single SoC (System-on-Chip) becomes feasible. The IP cores are connected via a bus, thus the preemption of bus among IP cores degrades the performance of SoC. Efficient bus arbiters can deal with the contentions and conflicts caused by the preemption of bus, and in this way the performance of SoC is improved. An improved high-speed lottery bus arbiter is proposed. The lottery decision mechanism deploys four-phase dual-rail protocol rather than clock to avoid the loss of tickets, and it utilizes cross parallel working manner of asynchronous pipeline to improve the working speed. In the NINP (NonIdling and NonPreemptive) model, simulations and verifications are made on Xilinx Virtex5 of 65 nm CMOS. The results show that compared with the commonly-used lottery arbiter and adaptive dynamic lottery arbiter, the proposed arbiter is better in output bandwidth allocation and can avoid starvation and monopolization of bus. Furthermore, the working speed increases by over 49.2% and it has advantages in power consumption. Thus it can be applied to multi-core SoC, which has requirements in working speed.