A Physical Design Approach for Mitigating Soft Errors in SRAM-based FPGAs

To solve the problem of soft error caused by Single Event Upset (SEU) in Static Random Access Memory (SRAM)-based Field Programmable Gate Arrays (FPGAs), the impact of routing resources by Single Bit Upset (SBU) and Multiple Bit Upset (MBU) is analyzed. A new method of soft-error-mitigation physical design approach is presented. In the approach, the error probability of routing resources is introduced for evaluation soft error. Combined with error propagation probability, system failure rate is calculated for driving placement and routing. The experimental results show that the system failure rate decreases about 18% using proposed method. This method can also effectively mitigate effect of multiple bit upset.