A 3D IC Self-test and Recovery Method Based on Through Silicon Via Defect Modeling

Through Silicon Via (TSV) is the key technology for vertical interconnections in 3D ICs, with insulator short and bump open being the two major types of TSV defects. In this paper, a TSV defect model is presented and the relationships between the linear oxide resistance/bump resistance and the TSV dimension are discussed. Based on the model, a method is proposed for detecting the voltage of the defects resistance. To verify the proposed method, a self-test circuit which can detect both types of defects is designed, and it can be cascaded to achieve auto-recovery on chip. Then, the area overhead is analyzed and the results show that self-test/recovery circuits will occupy lower percentage of total chip area as CMOS/TSV fabrication technology scales down or as TSV array size increases.