FPGA-based Design of LDPC Encoder with Throughput over 10 Gbps

This paper presents a high-throughput encoding method for IEEE 802.16e-like Low-Density Parity- Check (LDPC) codes. It is based on a fast double-recursion pipeline method, and can significantly improve the encoding speed. For more parallelism and less storage consumption, a partially-parallel architecture is designed. Furthermore, the storage system is optimized for parallel multi-frame coding, and the data storage unit and RAM address generator are shared for improving resource utilization. Design results are provided for an implementation on a Xilinx XC4VLX40 FPGA for codes with code length 2304 bit. It is shown that the proposed method can achieve a throughput in excess of 10 Gbps under a maximum clock frequency of 200 MHz, with the requirement of no more than 15% gate area and about 50% RAM storage.