Logic Equivalent Transformation for Nano-meter CMOS Hybrid Circuits

Regarding the connectivity domain constraint in nano-meter circuit architecture, this paper proposes a circuit equivalent transformation method based on logic replication for reducing mapping complexity. The fanout degrees of all gates in a circuit are recorded and sorted to select the reference of high fanout value. Then a quadratic equation is formulated to evaluate whether the mapping complexities of the gates are reduced. Finally, the gate which has fanout degree larger than the reference high fanout value will be replicated if the complexity degree is reduced. The proposed method can not only make circuits easily to map, but also achieve better timing than buffer insertion.