Hardware-efficient Motion Compensation Architecture for Multi-standard Video Decoder

To solve the problem of Motion Compensation (MC) for multiple standards efficiently, a modified hardware-efficient computing architecture of MC interpolation for multiple standards is developed with the proposed Rounding Last (RL) and Diagonal Two Step (DTS) strategies. A re-configurable MC interpolation hardware based on the new computing architecture is implemented efficiently based on the variable block size. Compared with the fixed-size 44 block-based MC in JM8.4, the bandwidth reduction is about 27%~50%, and the average burst length of each access to the external memory is improved to 1.22~2.25 times longer. When work at 125 MHz, the MC hardware is capable to accomplish the real-time decoding of video streams of the supported standards at 1080 p (19201080) 30 f/s.