Zhao Fei, Zhang Lu, Zhang Zhi-Yong, Lu Huan-Zhang. A Hardware Acceleration Based Algorithm for Real-time Binary Image Connected-component Labeling[J]. Journal of Electronics & Information Technology, 2011, 33(5): 1069-1075. doi: 10.3724/SP.J.1146.2010.00793
Citation:
Zhao Fei, Zhang Lu, Zhang Zhi-Yong, Lu Huan-Zhang. A Hardware Acceleration Based Algorithm for Real-time Binary Image Connected-component Labeling[J]. Journal of Electronics & Information Technology, 2011, 33(5): 1069-1075. doi: 10.3724/SP.J.1146.2010.00793
Zhao Fei, Zhang Lu, Zhang Zhi-Yong, Lu Huan-Zhang. A Hardware Acceleration Based Algorithm for Real-time Binary Image Connected-component Labeling[J]. Journal of Electronics & Information Technology, 2011, 33(5): 1069-1075. doi: 10.3724/SP.J.1146.2010.00793
Citation:
Zhao Fei, Zhang Lu, Zhang Zhi-Yong, Lu Huan-Zhang. A Hardware Acceleration Based Algorithm for Real-time Binary Image Connected-component Labeling[J]. Journal of Electronics & Information Technology, 2011, 33(5): 1069-1075. doi: 10.3724/SP.J.1146.2010.00793
Due to the requirement for real-time image processing in optical imaging homing weapon systems, this paper proposes a hardware acceleration based connected-component labeling algorithm, which is a real time and two-pass algorithm. The algorithm integrates the merit of pixel-based and the run-based algorithm, which sets pixel as scan unit and line as label unit. Tree-shape topology is constructed in the first scan process, and lines are exported as the results. Then the labels are replaced in the second scan process to complete the connected-component labeling. Experiments on DSP+FPGA platform demonstrate that the hardware acceleration implementation of algorithm reaches a higher performance and efficiency with less resources consumption, and meet the demand of real-time processing.