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Volume 32 Issue 4
Dec.  2010
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Hao Zhi-gang, Yang Hai-gang, Zhang Chong, Wu Qi-song, Yin Tao. An Improved Digital Decimation Filter for Sigma-Delta ADC[J]. Journal of Electronics & Information Technology, 2010, 32(4): 1012-1016. doi: 10.3724/SP.J.1146.2009.00247
Citation: Hao Zhi-gang, Yang Hai-gang, Zhang Chong, Wu Qi-song, Yin Tao. An Improved Digital Decimation Filter for Sigma-Delta ADC[J]. Journal of Electronics & Information Technology, 2010, 32(4): 1012-1016. doi: 10.3724/SP.J.1146.2009.00247

An Improved Digital Decimation Filter for Sigma-Delta ADC

doi: 10.3724/SP.J.1146.2009.00247
  • Received Date: 2009-03-02
  • Rev Recd Date: 2009-07-22
  • Publish Date: 2010-04-19
  • Usually in a sigma-delta ADC, the digital filter takes most of the chip area. In this paper, a novel digital filer topology is proposed, in which the differentiator is constructed with a control unit and an adder instead of the multiple of adders in the Hogenauer structure filter, so that the digital circuit area should be reduced. A fourth order digital filter employing such topology is implemented in a Cyclone-II FPGA, and costs chip resources 29 percent less than in a Hogenauer structure.
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