A Novel Algorithm for Circuit Partitioning at Transistor Level

Kernighan B W and Lin S. An efficient heuristic procedurefor partitioning graphs. The Bell System Technical Journal,1970, 49(1): 291-307.[2]Schweikert D G and Kernighan B W. A proper model for thepartitioning of electrical circuits. Proc. of 9th ACM/IEEEDesign Automation Conf., New York, 1972: 57-62.[3]Fiduccia C M and Mattheyses R M. A linear-time heuristicfor improving network partitions. Proc. of 19th ACM/IEEEDesign Automation Conf., Piscataway, NJ, 1982: 175-181.[4]Krishnamurthy B. An improved min-cut algorithm forpartitioning VLSI networks[J].IEEE Transactions onComputers.1984, 33(5):438-446[5]Sanchis L A. Multiple-way network partitioning[J].IEEETransactions on Computers.1989, 38(1):62-81[6]Dasdan A and Aykanat C. Two novel multiway circuitpartitioning algorithms using relaxed locking[J].IEEETransactions on Computer-aided Design of IntegratedCircuits and Systems.1997, 16(2):169-178[7]Frohlich N, Glockel V, and Fleischmann J. A newpartitioning method for parallel simulation of VLSI circuitson transistor level. Proc. of Design, Automation and Test inEurope Conference and Exhibition, Paris, 2000: 679-684.[8]Li J and Behjat L. Net cluster: A net-reduction-basedclustering preprocessing algorithm for partitioning andplacement[J].IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems.2007, 26(4):669-679[9]Bazylevych R, Podolskyy I, and Bazylevych L. Partitioningoptimization by recursive moves of hierarchically builtclusters. Proc. of Design and Diagnostics of ElectronicCircuits and Systems, Krakow, 2007: 1-4.Behjat L, Li J, and Huang J. Two clustering preprocessingtechniques for large-scale circuits. Proc. of Circuits andSystems, New Orleans, 2007: 1057-1060.[10]Leinweber L and Bhunia S. Fine-grained supply gatingthrough hypergraph partitioning and shannon decompositionfor active power reduction. Proc. of Design, Automation andTest in Europe, Munich, 2008: 373-378.Shan Y and Lin B. Application-specific Network-on-Chiparchitecture synthesis based on set partitions and SteinerTrees. Proc. of Design Automation Conference, SamFrancisco, 2008: 277-282.