Li Jian-wei, Dong Gang, Yang Yin-tang, Wang Zeng. Statistical RLC Interconnect Delay Considering Process Variations[J]. Journal of Electronics & Information Technology, 2009, 31(11): 2767-2771. doi: 10.3724/SP.J.1146.2009.00031
Citation:
Li Jian-wei, Dong Gang, Yang Yin-tang, Wang Zeng. Statistical RLC Interconnect Delay Considering Process Variations[J]. Journal of Electronics & Information Technology, 2009, 31(11): 2767-2771. doi: 10.3724/SP.J.1146.2009.00031
Li Jian-wei, Dong Gang, Yang Yin-tang, Wang Zeng. Statistical RLC Interconnect Delay Considering Process Variations[J]. Journal of Electronics & Information Technology, 2009, 31(11): 2767-2771. doi: 10.3724/SP.J.1146.2009.00031
Citation:
Li Jian-wei, Dong Gang, Yang Yin-tang, Wang Zeng. Statistical RLC Interconnect Delay Considering Process Variations[J]. Journal of Electronics & Information Technology, 2009, 31(11): 2767-2771. doi: 10.3724/SP.J.1146.2009.00031
Analysis of RLC Statistical delay considering process fluctuation is presented in this paper. Construction of parasitic parameters and moments with process variation is first given, and then a statistical delay model based on Weibull distribution is achieved. The proposed method is also applied to the other available delay such as Elmore, equivalent Elmore and D2M. For the statistical delay model based on Weibull distribution, compared with HSPICE, results show that the maximum error of 50% delay is 0.11%, the maximum error of mean and the average in Monte Carlo analysis is 2.02%.