A Selective Registering Technique for Design of an Embedded Programmable Memory

A selective registering method is proposed to solve the problem of data loss in readout caused by simultaneously accessing both the read and write ports at the same address of a synchronous dual-port memory IP. Using this method to design an embedded programmable memory with the synchronous dual-port memory IP gives rise to reducing the implementing complexity and further improving the designs migration capabilities. Thus the research and development time can be shortened dramatically. According to the measurement results, such an embedded programmable memory fabricated in SMIC 0.18 ?m 1P6M CMOS process has achieved some comparable performance for the compatible functions with the reference to those full custom embedded programmable memories based on the close processes.