Scheme of Fast Self-Calibration for a FPGA Chip Clock Generator

Dong Fang-yuan; Yang Hai-gang; Wei Yuan-feng

doi:10.3724/SP.J.1146.2008.00553

Volume 31 Issue 6

Jun. 2009

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Article Navigation > Journal of Electronics & Information Technology > 2009 > 31(6): 1521-1524

Dong Fang-yuan, Yang Hai-gang, Wei Yuan-feng. Scheme of Fast Self-Calibration for a FPGA Chip Clock Generator[J]. Journal of Electronics & Information Technology, 2009, 31(6): 1521-1524. doi: 10.3724/SP.J.1146.2008.00553

Citation:

Dong Fang-yuan, Yang Hai-gang, Wei Yuan-feng. Scheme of Fast Self-Calibration for a FPGA Chip Clock Generator[J]. Journal of Electronics & Information Technology, 2009, 31(6): 1521-1524. doi: 10.3724/SP.J.1146.2008.00553

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Scheme of Fast Self-Calibration for a FPGA Chip Clock Generator

doi: 10.3724/SP.J.1146.2008.00553

Received Date: 2008-05-05
Rev Recd Date: 2008-11-04
Publish Date: 2009-06-19

Abstract

Abstract

This paper presents a novel PLL self-calibration scheme based on Frequency-to-Voltage (F2V) Converting technique, which is fast and applicable for the Phase-Locked Loop(PLL) using a multi-band ring Voltage Controlled Oscillator (VCO) in the clock generation module of a FPGA device. Designs of key modules in the self-calibration circuit are detailed, and simulation of the full system is performed. Simulation results indicate that the system can self-calibrate quickly and properly in case of process variation or reference frequency switch. The clock generator using the proposed self-calibration circuit can obtain a wide frequency operating range while maintaining a relatively low VCO gain and it locks fast, as make it suitable for FPGA clock generation.

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References(1)

References

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