Research on SPMs Energy Model for Low Power Compilation

In order to achieve a better application effect of Scratch-Pad Memory(SPM), it,s appropriate to construct a proper SPMs performance and power-consumption model to guide the compiling optimization process. The existing power-consumption modeling can only provide SPM,s average access power-consumption which didnt reflect the characteristic that the actual circuits power-consumption varied as the input varied. It restricts further optimization. This thesis proposes to construct SPMs basic power-consumption modeling according to the circuit structure and generate modeling,s parameters based on program,s runtime information. These can reflect the circuits actual active degree when different programs executed. Shown in the experiment, the power-consumption measured is basically as accurate as the one that based on the existing statistical method on average. Furthermore, the new modeling can reflect the difference of power-consumption when different programs access SPM. This technique has an important guiding significance to the access mode as the compliers optimize SPM.