An Efficient DWT-EBCOT Combined VLSI Architecture with Low Memory for JPEG2000

Guo Jie; Li Yun-song; Wu Cheng-ke; Liu Kai; Wang Ke-yan

doi:10.3724/SP.J.1146.2007.01637

Volume 31 Issue 3

Dec. 2010

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Article Navigation > Journal of Electronics & Information Technology > 2009 > 31(3): 731-735

Guo Jie, Li Yun-song, Wu Cheng-ke, Liu Kai, Wang Ke-yan. An Efficient DWT-EBCOT Combined VLSI Architecture with Low Memory for JPEG2000[J]. Journal of Electronics & Information Technology, 2009, 31(3): 731-735. doi: 10.3724/SP.J.1146.2007.01637

Citation:

Guo Jie, Li Yun-song, Wu Cheng-ke, Liu Kai, Wang Ke-yan. An Efficient DWT-EBCOT Combined VLSI Architecture with Low Memory for JPEG2000[J]. Journal of Electronics & Information Technology, 2009, 31(3): 731-735. doi: 10.3724/SP.J.1146.2007.01637

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An Efficient DWT-EBCOT Combined VLSI Architecture with Low Memory for JPEG2000

doi: 10.3724/SP.J.1146.2007.01637

Received Date: 2007-10-16
Rev Recd Date: 2008-01-30
Publish Date: 2009-03-19

Abstract

Abstract

Motivated by an enormous amount of storage between DWT and EBCOT in JPEG2000 hardware implementation, a novel memory-efficient scheme based on code block size is proposed. Further reuse of on-chip code block size memories and efficient scheduling of them reduce hardware cost in both area and power. In the implementation, line-based lifting DWT architecture and bit plane parallel EBCOT design are used. The resulting coding efficiency is improved and the whole architecture can achieve real time processing. Experimental results show that on demand of real time coding, when a tile with resolution up to 512-width and 512-height is decomposed with four levels in 9/7 or 5/3 filters and the size of code block is 3232, the wavelet coefficients memory needed in the proposed architecture is reduced by over 80%, compared with existing architectures that wavelet coefficients are directly deposited in off-chip memories. The whole design has been synthesized and mapped into Xilinx FPGA, passing the verification when the system is working at the clock of 100MHz.

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References(1)

References

ISO/IEC JTC 1/SC 29/WG N1646R, ISO/IEC FCD15444-1.JPEG2000 Part Final Committee Draft Version 1.0 [S]. 16March 2000.[2]Daubechies I and Sweldens W. Factoring wavelet transforminto lifting steps [J].J. Fourier Anal. Applicat.1998, 4(2):247-269[3]Chiang Jen-Shiun, Lin Yu-Sen, and Hsieh Chang-Yo.Efficient pass-parallel architecture for EBCOT in JPEG2000[C]. Proceedings of IEEE International Symposium Circuitsand Systems, Scottsdale, Arizona, USA, 2002, I: 773-776.[4]Lian Chung-Jr, Chen Kuan-Fu, and Chen Hong-Hui, et al..Analysis and architecture design of block-coding engine forEBCOT in JPEG2000 [J].IEEE Trans. on Circuits andSystem for Video Technology.2003, 13(3):219-230[5]Acharya T and Chakrabarti C. A survey on lifting-baseddiscrete wavelet transform architectures [J]. Journal of VLSISignal Processing, 2006, 42(3): 321-339.[6]Cheung Ngai-Man, Tang C, and Ortega A, et al.. Efficientwavelet-based predictive Slepian-Wolf coding forhyperspectral imagery [J]. Eurasip Journal on Applied SignalProcessing, 2005, 86(11): 3180-3195.[7]Andra K, Chakrabarti C, and Acharya T. A highperformanceJPEG2000 architecture [J].IEEE Trans. onCircuits and System for Video Technology.2003, 13(3):209-218[8]Huang Quanping, Zhou Rongzheng, and Hong Zhiliang. Lowmemory and low complexity VLSI implementation ofJPEG2000 codec [J].IEEE Trans. on Consumer Electronics.2004, 50(2):638-646

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