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Volume 31 Issue 2
Dec.  2010
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Meng Tao, Dai Zi-bin. Reconfigurable Clustered Architecture of Block Cipher Processor[J]. Journal of Electronics & Information Technology, 2009, 31(2): 453-456. doi: 10.3724/SP.J.1146.2007.01586
Citation: Meng Tao, Dai Zi-bin. Reconfigurable Clustered Architecture of Block Cipher Processor[J]. Journal of Electronics & Information Technology, 2009, 31(2): 453-456. doi: 10.3724/SP.J.1146.2007.01586

Reconfigurable Clustered Architecture of Block Cipher Processor

doi: 10.3724/SP.J.1146.2007.01586
  • Received Date: 2007-09-29
  • Rev Recd Date: 2008-04-07
  • Publish Date: 2009-02-19
  • This paper presents the reconfigurable clustered architecture of block cipher processor. Appointed by instructions, the data-path of this architecture can be dynamically configured to be three modes, which includes 4clusters, 2clusters and single cluster mode. In different mode, different operations can be done, which improves the flexibility of this processor. Basing on clustered architecture, Explicit-decomposition low-power-design method is presented, which can reduce the power by 36.1%. With 5stages pipeline and wave-pipeline, this processor can work in a high rate. And the performances of AES/DES/IDEA reach 689.6Mbit/s, 400Mbit/s, 416.7Mbit/s.
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