ABCD Modeling of Crosstalk Coupling Noise of Interconnects

Palit Ajoy K and Anheier Walter. Reduced order longinterconnect modeling. Proc. of 15th GI/GMM/ITGWorkshop on Testmethoden und ZuverLassigkeit vonSchaltungen und Systemen, 23-25, Timmendorfer Strand,Germany, 23.03.2003 . 25.03 2003: 42-47.[2]Palit Ajoy K and Anheier Walter. Estimation of signalintegrity loss through reduced order interconnect model. Proc.IEEE-SPI, Siena, Italy, 2003: 163-166.[3]Palit Ajoy K and Anheier Walter. Test pattern generationbased on predicted signal integrity loss through reduced orderinterconnect model. 16-ITG-GI-GMM-Workshop Testmethodenund Zuverl Sigkeit von Schaltungen und Systemen,Dresden, Germany, 29.02.2004-02.03.2004: 84-88.[4]Palit Ajoy K, Anheier Walter, and Meyer V. Modeling andanalysis of crosstalk coupling effect on the victiminterconnect using the ABCD network model. 19th IEEEInternational Symposium on Defect and Fault Tolerance inVLSI Systems, Cannes, France, 10-13. Oct. 2004: 174-182.[5]Palit Ajoy K, Anheier Walter, and Schloeffel J. A new,flexible and very accurate crosstalk fault model to analyze theeffects of coupling noise between the interconnects on signalintegrity losses in deep submicron chips. Proceedings of 14thIEEE-Asian Test Symposium, Calcutta, India, 18.12.2005 .21.12. 2005: 22-27.[6]Bogatin Eric 挊, 棝嬍嶳.. 怣崋姰惍惈暘愅. .巕岺.弌斉幮, 2006.1: 124-128.[7]Banerjee K and Mehrotra A. Analysis of on-chip inductanceeffects for distributed RLC interconnects[J].IEEE Trans. onCAD of Integrated Circuits and Systems.2002, 21(8):904-915