Built-in Self-Test Scheme for Path Delay Fault of Array Multiplier

Yang De-cai; Chen Guang-ju; Xie Yong-le

doi:10.3724/SP.J.1146.2007.01007

Volume 31 Issue 1

Dec. 2010

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Article Navigation > Journal of Electronics & Information Technology > 2009 > 31(1): 238-241

Yang De-cai, Chen Guang-ju, Xie Yong-le. Built-in Self-Test Scheme for Path Delay Fault of Array Multiplier[J]. Journal of Electronics & Information Technology, 2009, 31(1): 238-241. doi: 10.3724/SP.J.1146.2007.01007

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Yang De-cai, Chen Guang-ju, Xie Yong-le. Built-in Self-Test Scheme for Path Delay Fault of Array Multiplier[J]. Journal of Electronics & Information Technology, 2009, 31(1): 238-241. doi: 10.3724/SP.J.1146.2007.01007

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Built-in Self-Test Scheme for Path Delay Fault of Array Multiplier

doi: 10.3724/SP.J.1146.2007.01007

Received Date: 2007-06-22
Rev Recd Date: 2007-11-12
Publish Date: 2009-01-19

Abstract

Abstract

Due to high integration and high speed operation, array multiplier much likely suffers from delay fault. In this paper, a Built-In Self-Test (BIST) scheme is presented for the delay fault test of such array multiplier in which an accumulator is utilized as test pattern generator. Based on the transition propagation analysis of the basic unit of full adder, a kind of single input change BIST sequences is generated which has been designated to be more effective than multiple input change sequences when highly robust delay fault coverage is targeted in a series of previous theoretical and experimental results. The proposed scheme is well balanced between the path coverage and the number of test patterns. Simulation results demonstrate the proposed scheme can get high path coverage. Furthermore, the reuse of existing accumulator to generate test patterns can lead to low hardware overhead.

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References(1)

References

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