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Volume 30 Issue 9
Jan.  2011
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Yang Jun-Gang, Liu Zeng-Ji, Zhao Rui-Qin, Luo Xiao-Zhuo. A Scheduling Algorithm Based on Credit in Variable-length Packet Parallel Switching Network[J]. Journal of Electronics & Information Technology, 2008, 30(9): 2229-2232. doi: 10.3724/SP.J.1146.2007.00281
Citation: Yang Jun-Gang, Liu Zeng-Ji, Zhao Rui-Qin, Luo Xiao-Zhuo. A Scheduling Algorithm Based on Credit in Variable-length Packet Parallel Switching Network[J]. Journal of Electronics & Information Technology, 2008, 30(9): 2229-2232. doi: 10.3724/SP.J.1146.2007.00281

A Scheduling Algorithm Based on Credit in Variable-length Packet Parallel Switching Network

doi: 10.3724/SP.J.1146.2007.00281
  • Received Date: 2007-02-13
  • Rev Recd Date: 2007-09-19
  • Publish Date: 2008-09-19
  • A new scheduling algorithm in Parallel Packet Switch(PPS) is proposed in this paper . This algorithm eliminates out-of sequence of the cells belonging to a packet by dispatching the traffic with variable-length packet at de-multiplexer. It balances the traffic distribution to each parallel switch by a credit based mechanism. The combined input and output queued(CIOQ) mechanism is adopted with each parallel switch in this algorithm, which not only degrades the speed-up requirement of the buffer and switch, but also takes full advantage of the available research achievements of scheduling algorithm in Crossbar switches. Theoretical analysis is made on the fairness of traffic distributions, the amount of the required high-speed buffer (run in line-speed) and the stability of the network. The simulation analysis shows the good performance of this algorithm further.
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  • [1] Iyer S.[J].Awadallah A, and McKeown N. Analysis of a packetswitch with memories running slower than the line rate[C].IEEE INFOCOM 00, Tel-Aviv, Israel.2000,:- [2] Iyer S and McKeown N. Making Parallel Packet SwitchesPractical[C]. IEEE INFOCOM01, Alaska, USA, 2001: 1680-1687. [3] Zhong Hakhan, Xu Du, and Zhu Zhenyu. A parallel packetswitch supporting variable-length packets[C]. InternationalConference on Communications, Circuits and SystemsProceedings. Hong Kong, China, 2005: 613-617. [4] Shi Lei and Li Wenjie, et al.. Flow mapping in the loadbalancing parallel packet switches[C]. Workshop on HighPerformance Switching and Routing. Hong Kong, China,2005: 254-258. [5] Ganjali Y.[J].Keshavarzian A, and Shah D. Input queuedswitches: cell switching vs. packet switching[C]. IEEEINFOCOM03. San Francisco, USA.2003,:- [6] McKeown N. iSLIP: A scheduling algorithm for input-queuedswitches[J].IEEE/ACM Trans. on Networking.1999, 7(2):188-201 [7] Prabhakar B and McKeown N. On the speedup required forcombined input and output queued switching[J].Automatica.1999, 35(12):1909-1920 [8] Dai J G and Prabhakar B. The throughput of data switcheswith and without speedup[C]. IEEE INFOCOM00, TelAviv,Israel, 2000: 556-564. Goudreau M W.[J].et al.. Scheduling algorithms for input-queuedswitches: Randomized techniques and experimental evaluation[C]. IEEE INFOCOM00, TelAviv, Israel.2000,:-
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