A SRAM-less Deblocking Filter in H.264/AVC

A new VLSI architecture of deblocking filter is developed for H.264/AVC system. In the presented architecture, a novel filter scheduling is proposed to reduce the size of local data buffer, and an enhanced data reuse technology is adopted to reduce the number of external memory access, thus the speed of filtering process is significantly improved as well. Whats more, this architecture employs no on-chip SRAM, so there is no on-chip SRAM access. Simulation results show that the new filter can support real-time deblocking for HDTV video application when it works at 100 MHz. The synthesized logic gate count is only 16.8k with 0.18m CMOS technology.