Quan Yuan-yuan, Wang Pei, He Hong-lu, Yuan Xiao-bing, Zhu Ming-hua. VLSI Design of the Low-Power Rake Receiver for Wireless Sensor Networks[J]. Journal of Electronics & Information Technology, 2008, 30(8): 2017-2020. doi: 10.3724/SP.J.1146.2006.02089
Citation:
Quan Yuan-yuan, Wang Pei, He Hong-lu, Yuan Xiao-bing, Zhu Ming-hua. VLSI Design of the Low-Power Rake Receiver for Wireless Sensor Networks[J]. Journal of Electronics & Information Technology, 2008, 30(8): 2017-2020. doi: 10.3724/SP.J.1146.2006.02089
Quan Yuan-yuan, Wang Pei, He Hong-lu, Yuan Xiao-bing, Zhu Ming-hua. VLSI Design of the Low-Power Rake Receiver for Wireless Sensor Networks[J]. Journal of Electronics & Information Technology, 2008, 30(8): 2017-2020. doi: 10.3724/SP.J.1146.2006.02089
Citation:
Quan Yuan-yuan, Wang Pei, He Hong-lu, Yuan Xiao-bing, Zhu Ming-hua. VLSI Design of the Low-Power Rake Receiver for Wireless Sensor Networks[J]. Journal of Electronics & Information Technology, 2008, 30(8): 2017-2020. doi: 10.3724/SP.J.1146.2006.02089
A low-power VLSI Rake receiver is proposed and realized on FPGA for wireless sensor networks used in complicated wireless environments. Low-power design strategies including reducing clock frequency, sharing of models and dynamic sleeping control are used to reduce the power consumption in order to fit the energy limitations in wireless sensor networks. Simulations and applications show that the receiver can specially reduce VLSI resource and power consumption compared to ordinary Rake receiver.
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