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Volume 30 Issue 7
Jan.  2011
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Xu En-yang, Jiang Ming, Zhao Chun-ming . A Synchro Partially Parallel Architecture for Quasi-Cyclic LDPC Codes[J]. Journal of Electronics & Information Technology, 2008, 30(7): 1630-1634. doi: 10.3724/SP.J.1146.2006.01915
Citation: Xu En-yang, Jiang Ming, Zhao Chun-ming . A Synchro Partially Parallel Architecture for Quasi-Cyclic LDPC Codes[J]. Journal of Electronics & Information Technology, 2008, 30(7): 1630-1634. doi: 10.3724/SP.J.1146.2006.01915

A Synchro Partially Parallel Architecture for Quasi-Cyclic LDPC Codes

doi: 10.3724/SP.J.1146.2006.01915
  • Received Date: 2006-12-04
  • Rev Recd Date: 2007-05-21
  • Publish Date: 2008-07-19
  • Based on the structure of quasi-cyclic LDPC codes, a synchro partially parallel decoder is proposed in this paper. In the decoder, the check node process units and variable node process units work concurrently, where the new generated soft information is used in advance during the iteration process to accelerate the convergence speed. Furthermore, differential evolution is utilized to optimize the start positions of node process units in order to achieve better performance. Simulation results show that the proposed scheme outperforms others both in performance and complexity, and is very suitable for the implementation of high speed decoders.
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  • Gallager R G. Low-density parity-check codes. IRE Trans. onInform. Theory, 1962, 1(8): 21-28.[2]Blanksby A and Howland C. A 690-mw 1-Gbps 1024-bRate-1/2 low-density parity-check code decoder[J].IEEEJournal of Solid State Circuits.2002, 37(3):404-412[3]Zhang T and Parhi K K. A 54 Mbps (3, 6)-regular FPGALDPC decoder. IEEE Proc. of SIPS, San Diego, CA, USA,Oct. 2002: 127-132.[4]Chen Y and Parhi K K. Overlapped message passing forquasi-cyclic low density parity check codes[J].IEEE Trans. onCircuits and Systems.2004, 51(6):1106-1113[5]Shimizu K, Ishikawa T, and Togawa N, et al.. PartiallyparallelLDPC decoder achieving high-efficiency messagepassingschedule[J].IEICE Trans. on Fundamentals ofElectronics.2006, E89-A(4):969-978[6]Sridhara D, Fuja T, and Tanner R M. Low density paritycheck codes from permutation matrices. Proceedings of 2001Conference on Information Sciences and Systems, The JohnsHopkins University, March 2001: 21-23.[7]Li Z, Chen L, and Zeng L, et al.. Efficient encoding ofquasi-cyclic low-density parity-check codes[J].IEEE Trans. onCom.2006, 54(1):71-81[8]Price K and Storn R. Differential evolutionA simple andefficient heuristic for global optimization over continuousspaces. Journal of Global Optimize, 1997, 19(11): 341-359.[9]IEEE P802.16e/D12. IEEE standard for local andmetropolitan area networks-part 16: Air interface for fixedand mobile broadband wireless access systems (amendmentfor physical and medium access control layers for combinedfixed and mobile operation in licensed bands). IEEE, 2006.赵春明,许恩杨,姜明等. 双涡轮结构低密度奇偶校验码解码器.中国发明专利,申请号200610096535.9, 2006,9.
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