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Volume 29 Issue 11
Jan.  2011
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Hu Yun, Wang Ling-Li, Tang Pu-Shan, Tong Jia-Rong. A Circuit Partition Algorithm Basing on Probability Gain[J]. Journal of Electronics & Information Technology, 2007, 29(11): 2762-2766. doi: 10.3724/SP.J.1146.2006.00377
Citation: Hu Yun, Wang Ling-Li, Tang Pu-Shan, Tong Jia-Rong. A Circuit Partition Algorithm Basing on Probability Gain[J]. Journal of Electronics & Information Technology, 2007, 29(11): 2762-2766. doi: 10.3724/SP.J.1146.2006.00377

A Circuit Partition Algorithm Basing on Probability Gain

doi: 10.3724/SP.J.1146.2006.00377
  • Received Date: 2006-03-28
  • Rev Recd Date: 2006-08-25
  • Publish Date: 2007-11-19
  • This paper proposes a new partition algorithm. The variable weight of the nets is introduced into the algorithm. Generally, the nodes connected to the nets are more than two in the hypergraph, so the probability gain model is used to enforce the effect of the increased weight of the nets. This algorithm can jump out of local minimal effectively when compared with original algorithm. The improvement is especially obvious for the large-scale circuits. For the gain value of the cell is floating-point, balanced binary tree is used to store the gain value of the cells, so the speed of this algorithm is several times slower than FM algorithm. The time complexity of this algorithm is O(P log2(n))(where P is the sum of the pins of all logic cells of the circuit, and n is the number of the circuit logic cells).
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