Wu Shuang-yi, Yu Qi, Wang Hao-juan, Qin Hao-yang, Ning Ning, Yang Mo-hua. A Power-Conversion Rate Merit Model for High-Speed High-Resolution ADC[J]. Journal of Electronics & Information Technology, 2007, 29(8): 2006-2008. doi: 10.3724/SP.J.1146.2006.00122
Citation:
Wu Shuang-yi, Yu Qi, Wang Hao-juan, Qin Hao-yang, Ning Ning, Yang Mo-hua. A Power-Conversion Rate Merit Model for High-Speed High-Resolution ADC[J]. Journal of Electronics & Information Technology, 2007, 29(8): 2006-2008. doi: 10.3724/SP.J.1146.2006.00122
Wu Shuang-yi, Yu Qi, Wang Hao-juan, Qin Hao-yang, Ning Ning, Yang Mo-hua. A Power-Conversion Rate Merit Model for High-Speed High-Resolution ADC[J]. Journal of Electronics & Information Technology, 2007, 29(8): 2006-2008. doi: 10.3724/SP.J.1146.2006.00122
Citation:
Wu Shuang-yi, Yu Qi, Wang Hao-juan, Qin Hao-yang, Ning Ning, Yang Mo-hua. A Power-Conversion Rate Merit Model for High-Speed High-Resolution ADC[J]. Journal of Electronics & Information Technology, 2007, 29(8): 2006-2008. doi: 10.3724/SP.J.1146.2006.00122
Based on multi-stage comparison, a new theory incorporating Minimum Comparator Number Algorithm (MCNA) and Power-Conversion Rate Merit Model (PCRMM) is proposed, which releases the power dissipation from limitation of comparators, sub-DACs and residual amplifiers in high-speed high-resolution ADCs. Under 10-bit ADC resolution specific, theoretical analysis shows that this theory reduces the power dissipation of Flash ADC to minimum by applying 3-stage Pipelined ADC, while keeping ADC high-speed, and it also proves that two-step ADC is better than other type of multi-step ADC. This new theory can be used in designing and developing high-speed low-power ADCs.
Gray P R and Meyer R G. Future directions in silicon IC's for RF personal communications. Proc. IEEE Custom Integrated Circuits Conf.,Santa Clam. CA, USA, May 1995.[2]Stojcevski A.[J].Singh J, and Zayegh, et al.. Performances analysis of a CMOS analog to digital converter for wireless telecommunications. Proc. IEEE Devices Systems Conf, ISIC-2001, Singapore.2001,:-[3]Lewis S H. Optimizing the stage solution in pipelined, multistage, analog-to-digital converters for video-rate applications[J].IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing.1992, 39(8):516-523[4]Kwok P T F and Luong H C. Power optimization for pipeline analog-to-digital converters[J].IEEE Trans. on Circuits and System-II: Analog and Digital Signal Processing.1999, 46(5):549-553
DownLoad: