An Adaptive PLL Architecture to Achieve Fast Settling Time

Huang Shui-long; Wang Zhi-hua

doi:10.3724/SP.J.1146.2005.01548

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Huang Shui-long, Wang Zhi-hua. An Adaptive PLL Architecture to Achieve Fast Settling Time[J]. Journal of Electronics & Information Technology, 2007, 29(6): 1492-1495. doi: 10.3724/SP.J.1146.2005.01548

Citation:

Huang Shui-long, Wang Zhi-hua. An Adaptive PLL Architecture to Achieve Fast Settling Time[J]. Journal of Electronics & Information Technology, 2007, 29(6): 1492-1495. doi: 10.3724/SP.J.1146.2005.01548

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An Adaptive PLL Architecture to Achieve Fast Settling Time

doi: 10.3724/SP.J.1146.2005.01548

Received Date: 2005-11-28
Rev Recd Date: 2006-05-31
Publish Date: 2007-06-19

Abstract

Abstract

The relationships between loop performance (settling time, phase noise and spur signal) and loop parameters (bandwidth and phase margin) are briefly discussed in the paper. An adaptive Phase-Locked Loop (PLL) with a fast settling time and its key blocks including Phase-Frequency Detector (PFD) and charge pump are then proposed and analyzed. The proposed architecture is based on two tuning loops: a coarse-tuning loop and a fine-tuning loop. The coarse-tuning loop is used for fast convergence and the fine-tuning loop is used to complete fine adjustments. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside control signal. Spectre simulation based on SMIC 0.18m 1.8V supply voltage CMOS technology shows that coarse-tuning PFD can effectively cut off coarse-tuning loop, and the charge pump has a 0.1% up/down current mismatching characteristic. The adaptive PLL can reduce settling time over 30% in comparison to the conventional PLL in the same loop bandwidth.

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References(1)

References

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