Implementation of Folded-Cascode OTAs MST State via Clock Feedthrough Frequency Compensation

Wang Xiang-zhan; Ning Ning; Yu Qi; Dai Guang-hao; Yang Mo-hua

doi:10.3724/SP.J.1146.2005.01263

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Wang Xiang-zhan, Ning Ning, Yu Qi, Dai Guang-hao, Yang Mo-hua. Implementation of Folded-Cascode OTAs MST State via Clock Feedthrough Frequency Compensation[J]. Journal of Electronics & Information Technology, 2007, 29(3): 743-746. doi: 10.3724/SP.J.1146.2005.01263

Citation:

Wang Xiang-zhan, Ning Ning, Yu Qi, Dai Guang-hao, Yang Mo-hua. Implementation of Folded-Cascode OTAs MST State via Clock Feedthrough Frequency Compensation[J]. Journal of Electronics & Information Technology, 2007, 29(3): 743-746. doi: 10.3724/SP.J.1146.2005.01263

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Implementation of Folded-Cascode OTAs MST State via Clock Feedthrough Frequency Compensation

doi: 10.3724/SP.J.1146.2005.01263

Received Date: 2005-10-10
Rev Recd Date: 2006-03-27
Publish Date: 2007-03-19

Abstract

Abstract

In this article, a novel Clock Feedthrough Frequency Compensation (CFFC) method based on the Minimum-Settling-Time (MST) theory and step-response analysis of a second order system is presented. Cadence ADE simulation results of a folded-cascode OTA with CFFC designed with SMIC 0.35m 2P3M Polyside Si CMOS models show that the settling time of the CFFC compensated cascode OTA is reduced by 22.7%, MST state is obtained as well. With the capacitor load varies from 0.5pF to 2.5pF, the settling time changes linearly from 3.62ns to 4.46ns, and the circuit achieves MST state at each load value. This method can be applied to high-speed active switched capacitor networks and its related fields.

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References(1)

References

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