A Novel Arithmetic of Circuits Partition Used in Parallel Digital Simulation

Lv Meng; Fu  Yu-Zhuo

doi:10.3724/SP.J.1146.2005.01061

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Lv Meng , Fu Yu-Zhuo. A Novel Arithmetic of Circuits Partition Used in Parallel Digital Simulation[J]. Journal of Electronics & Information Technology, 2007, 29(4): 1009-1012. doi: 10.3724/SP.J.1146.2005.01061

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Lv Meng , Fu Yu-Zhuo. A Novel Arithmetic of Circuits Partition Used in Parallel Digital Simulation[J]. Journal of Electronics & Information Technology, 2007, 29(4): 1009-1012. doi: 10.3724/SP.J.1146.2005.01061

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A Novel Arithmetic of Circuits Partition Used in Parallel Digital Simulation

doi: 10.3724/SP.J.1146.2005.01061

Lv Meng ,
Fu Yu-Zhuo

Received Date: 2005-08-25
Rev Recd Date: 2005-12-29
Publish Date: 2007-04-19

Abstract

Abstract

Parallel simulation techniques are often employed to meet the computational requirements of large hardware simulations in order to reduce simulation time. In addition, partitioning for parallel simulations has been shown to be vital for achieving higher simulation throughput. This paper presents the design and implementation of a new partitioning algorithm based on a multilevel heuristic, also presents the speed up of applying this to a real hardware parallel simulation system Discovery. This algorithm attempts to balance load and reduce the whole simulation network communication to improve performance. The experimental results obtained from the benchmarks indicate that this algorithm yields better partitions than other partitioning algorithms for better simulation performance.

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References

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