DSC-PUF: Dynamic Spatial Coupling Strong PUF Circuit Against Machine Learning Attacks

HU Shuang; WANG Pengjun; ZHOU Zhenkai; ZHANG Yuejun; FANG Zhen

doi:10.11999/JEIT261012

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HU Shuang, WANG Pengjun, ZHOU Zhenkai, ZHANG Yuejun, FANG Zhen. DSC-PUF: Dynamic Spatial Coupling Strong PUF Circuit Against Machine Learning Attacks[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT261012

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HU Shuang, WANG Pengjun, ZHOU Zhenkai, ZHANG Yuejun, FANG Zhen. DSC-PUF: Dynamic Spatial Coupling Strong PUF Circuit Against Machine Learning Attacks[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT261012

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DSC-PUF: Dynamic Spatial Coupling Strong PUF Circuit Against Machine Learning Attacks

doi: 10.11999/JEIT261012 cstr: 32379.14.JEIT261012

1.
School of Integrated Circuits, Ningbo University, Ningbo 315211, China
2.
College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou 325035, China

Funds: The National Natural Science Foundation of China (62234008, 62474100), The Zhejiang Provincial Science and Technology Program “Pioneer and Leading Goose + X” Project (2025C01063), The Key R&D Program of Ningbo Science and Technology Yongjiang 2035 (2024Z139)

Accepted Date: 2026-10-16
Rev Recd Date: 2026-10-16

Available Online: 2026-10-29

Abstract

Abstract

Objective The large-scale deployment of Internet of Things (IoT) devices raises the demand for lightweight authentication and dynamic key generation on resource-limited hardware. Physical Unclonable Functions (PUFs) leverage inherent manufacturing variations of integrated circuits to generate unique, unclonable hardware fingerprints, serving as an effective lightweight scheme for device authentication and secure key derivation. Nevertheless, conventional delay-based strong PUFs feature linear delay superposition, rendering their challenge–response relationships susceptible to machine learning modeling. Existing countermeasures against modeling attacks enhance nonlinearity using elaborate feedback loops, multi-stage XOR gates and heterogeneous logic cells. Though these approaches improve security to some extent, they incur substantial hardware overhead, timing convergence problems, degraded reliability and weak environmental robustness. This work presents a Dynamic Spatial Coupling Strong PUF (DSC-PUF) architecture. With restrained hardware cost, the proposed design maintains PUFs’ inherent physical properties and resistance to machine learning attacks, enabling joint optimization of multi-dimensional system metrics. Methods To mitigate modeling vulnerabilities of conventional strong PUFs and resolve the tradeoff between security and reliability, this paper presents a DSC-PUF architecture with dual delay chains and dynamic spatial perturbation. It consists of a primary chain A, an auxiliary chain B, and a dynamic spatial coupling network. As signals propagate, the primary chain captures multi-level delay competition outcomes to produce random hidden states governed by physical process variations. Using these hidden states as dynamic control signals, nonlinear transformations including mask modulation, long-range shift diffusion, and symmetric interleaved XOR are applied to input challenges. This dynamically varies the challenge space seen by the auxiliary chain and breaks the stable linear CRP mapping inherent in traditional PUFs. To suppress dynamic interference to system stability, a master-slave asynchronous triggering mechanism is introduced. It temporally isolates hidden state latching, spatial coupling and auxiliary-chain propagation to prevent glitch propagation and race hazards. A majority voting scheme is also utilized for response denoising to enhance output robustness under harsh operating conditions. Results and Discussions The proposed architecture was implemented on a Xilinx Artix-7 FPGA platform, and its performance was evaluated through multiple standard tests. Experimental results demonstrate that the DSC-PUF significantly enhances the resistance of conventional delay-based PUFs against machine learning modeling attacks. Under typical attacks, including Logistic Regression, Support Vector Machine, Deep Neural Network, Covariance Matrix Adaptation Evolution Strategy, Convolutional Neural Network, and Light Gradient Boosting Machine, the prediction accuracy remains between 50.28% and 53.39%, close to the random-guessing level (Fig. 5), indicating that the dynamic spatial reconfiguration mechanism effectively disrupts the stable feature distribution of conventional CRPs. The proposed structure has a minimum reliability of 98.49% in the temperature range of -40℃ to 80℃, satisfying the reliability requirements of IoT devices in complex environments (Fig. 6). The generated responses successfully passed the NIST SP800-22 randomness test suite (Table 1 and Fig. 7), while the autocorrelation coefficients remained within the 95% confidence bounds of ±0.0141 (Fig. 8), demonstrating favorable randomness and low data correlation. In addition, the proposed architecture achieved a uniqueness value of 0.5152 and an average Strict Avalanche Criterion value of approximately 0.517 (Fig. 9 and 10), both close to the theoretical ideal values. The hardware overhead of the proposed design is 606 LUTs and 350 FFs (Table 2), demonstrating good lightweight implementation efficiency. Compared with existing strong PUF structures, the proposed DSC-PUF achieves a better balance among attack resistance, reliability, randomness, and hardware overhead. Conclusions This paper proposes a dynamic spatial coupling strong PUF architecture with enhanced resistance against machine learning attacks. By introducing a hidden-state-driven dynamic spatial coupling mechanism, the proposed architecture dynamically reconstructs challenge features, thereby disrupting the stable linear characteristics of conventional delay-based PUFs and reducing the statistical learnability of challenge–response mappings. Experimental results demonstrate that the DSC-PUF effectively resists LR, SVM, DNN, CMA-ES, CNN, and LightGBM modeling attacks, with prediction accuracies reduced to near-random guessing levels, while maintaining favorable reliability, randomness, uniqueness, and avalanche characteristics. This architecture provides a reliable hardware security solution for device authentication and secure key generation in resource-constrained IoT environments.

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References(24)

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