A Low-Power CNN/SNN Hybrid Hardware Accelerator with Configurable Time-Window Architecture

LI Qikang; ZHANG Yuejun; WANG Lixun; ZHANG Huihong; WANG Pengjun; XIE Wei; SU Binjie

doi:10.11999/JEIT260926

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LI Qikang, ZHANG Yuejun, WANG Lixun, ZHANG Huihong, WANG Pengjun, XIE Wei, SU Binjie. A Low-Power CNN/SNN Hybrid Hardware Accelerator with Configurable Time-Window Architecture[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260926

Citation:

LI Qikang, ZHANG Yuejun, WANG Lixun, ZHANG Huihong, WANG Pengjun, XIE Wei, SU Binjie. A Low-Power CNN/SNN Hybrid Hardware Accelerator with Configurable Time-Window Architecture[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260926

Citation:

LI Qikang, ZHANG Yuejun, WANG Lixun, ZHANG Huihong, WANG Pengjun, XIE Wei, SU Binjie. A Low-Power CNN/SNN Hybrid Hardware Accelerator with Configurable Time-Window Architecture[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260926

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A Low-Power CNN/SNN Hybrid Hardware Accelerator with Configurable Time-Window Architecture

doi: 10.11999/JEIT260926 cstr: 32379.14.JEIT260926

1.
School of Integrated Circuit, Ningbo University, Ningbo 315211, China
2.
College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou, Zhejiang 325035, China
3.
Department of Cardiology, Haishu District People’s Hospital, Ningbo 315211, China

Funds: The Key R&D Program of Cixi (CZ2025006), the Ningbo University “Double First-Class” Cooperation Special Directional Entrusted Scientific and Technological Cooperation Project under Grant (HX2024000574, HX2025000106) and Ningbo Municipal Health and Healthcare Science Technology Programme Projects (2024Y27, 2025Y26)

Accepted Date: 2026-10-16
Rev Recd Date: 2026-10-16

Available Online: 2026-10-29

Abstract

Abstract

In recent years, hybrid convolutional neural network (CNN) and spiking neural network (SNN) accelerators have shown great potential for edge intelligence. However, existing designs typically employ fixed time windows (TW) for temporal integration, limiting their adaptability to tasks with different temporal complexities. This work presents a low-power hybrid CNN/SNN accelerator with configurable TWs. First, a configurable TW instruction set is developed based on the spatiotemporal complexity of different tasks to reduce inference latency and computational overhead. Second, a zero-skipping data-reuse processing array with unified CNN/SNN operator mapping is designed to improve computational resource utilization. Finally, an event-driven execution scheme and fine-grained clock-gating strategy are introduced to eliminate redundant operations and memory accesses during computation and data transfer. The proposed CNN/SNN accelerator is fabricated in a 28-nm TSMC CMOS process, occupying a core area of 0.75 mm². At 0.81 V and 100 MHz, it achieves classification accuracies ranging from 75.3% to 98.4% across MIT-BIH, N-TIDIGITS, N-MNIST, IMAGE-100, and UniMiB SHAR, with a minimum energy consumption of 147.78 nJ per inference. Compared with prior works, the configurable-TW mechanism reduces energy consumption by 1.24×–7.6× while maintaining competitive classification accuracy, significantly improving the overall energy efficiency. Objective The goal of this work is to design an efficient and low-power CNN/SNN hybrid neuromorphic SoC based on the RISC-V architecture, addressing the limitations of conventional SNN hardware with fixed TW under different task requirements. By introducing a configurable TW mechanism, the temporal integration length can be flexibly adjusted according to task complexity, thereby reducing redundant time-step computations and lowering inference latency and energy consumption. Methods To address the varying time-window requirements of different tasks, this work presents a RISC-V-based SCNN processor with a configurable TW. First, a custom instruction set is developed to configure the TW threshold of the underlying hardware according to the complexity of input samples, enabling demand-driven computation while reducing inference latency and computational overhead. Second, a zero-skipping data-reuse processing array is designed to improve computational resource utilization. Finally, an event-driven execution mechanism and fine-grained clock-gating strategy are introduced to eliminate redundant operations and unnecessary memory accesses during computation and data transfer. The chip is fabricated in a 28-nm TSMC CMOS process with a core area of 0.75 mm². Across MIT-BIH, N-TIDIGITS, N-MNIST, IMAGE-100, and UniMiB SHAR tasks, the accelerator achieves classification accuracies ranging from 75.3% to 98.4%, with a minimum energy consumption of 147.78 nJ per inference. Results and Discussions Experimental results validate the effectiveness of the proposed configurable-TW SCNN processor under diverse workloads. Cross-task analysis (Fig. 7) shows that accuracy generally improves with increasing TW, but sensitivity varies significantly across tasks. Event-driven datasets such as N-MNIST and UniMiB SHAR exhibit strong temporal redundancy, achieving near-saturated accuracy (97.8%–98.4%) at small TW (≥3), whereas temporally dependent tasks like N-TIDIGITS require larger TW to maintain performance, indicating that TW demand is inherently data-modality dependent. Single-task evaluation (Fig. 8 and Fig. 9) further demonstrates that reducing TW can significantly lower spike rates and computational cost with negligible accuracy degradation. The latency–accuracy trade-off (Fig. 10) reveals that blindly increasing TW leads to exponential growth in addition operations and inference latency without proportional accuracy gains. The optimal TW varies across tasks, highlighting the necessity of dynamic TW adaptation. Conclusions This work presents a hybrid hardware accelerator with a configurable TW. By dynamically adjusting the TW, the proposed design addresses the performance and energy-efficiency limitations of fixed temporal resolution in conventional SNN hardware. Implemented in a TSMC 28-nm process, the accelerator occupies a core area of only 0.75 mm² and supports multimodal tasks, including physiological-signal, speech, visual, and activity recognition. It achieves classification accuracies of 75.3%–98.4% and a minimum energy consumption of 147.78 nJ per inference. Compared with fixed-TW designs, the proposed accelerator offers greater task adaptability, computational efficiency, and energy efficiency, reducing energy consumption by 1.24×–7.6× under the same process technology.
- Configurable time window,
- Spiking neural network,
- RISC-V,
- Hardware accelerator

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References(18)

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