Asymmetric Step 4H-SiC MOSFET with Integrated Reverse Channel

SHANG Shiguang; JIA Wei; WEI Jiarui; MA Jintao; CHEN Qing

doi:10.11999/JEIT260907

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SHANG Shiguang, JIA Wei, WEI Jiarui, MA Jintao, CHEN Qing. Asymmetric Step 4H-SiC MOSFET with Integrated Reverse Channel[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260907

Citation:

SHANG Shiguang, JIA Wei, WEI Jiarui, MA Jintao, CHEN Qing. Asymmetric Step 4H-SiC MOSFET with Integrated Reverse Channel[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260907

SHANG Shiguang, JIA Wei, WEI Jiarui, MA Jintao, CHEN Qing. Asymmetric Step 4H-SiC MOSFET with Integrated Reverse Channel[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260907

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Asymmetric Step 4H-SiC MOSFET with Integrated Reverse Channel

doi: 10.11999/JEIT260907 cstr: 32379.14.JEIT260907

School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China

Funds: Technology Project of Shaanxi Province, China (Grant Nos. 2026CY-YBXM-062)

Received Date: 2026-07-02
Accepted Date: 2026-10-16
Rev Recd Date: 2026-09-29

Available Online: 2026-10-22

Abstract

Abstract

Objective Featuring superior material properties including high thermal conductivity, high critical breakdown electric field, and high electron saturation velocity, 4H-SiC MOSFETs break through the performance bottlenecks of conventional silicon-based MOSFETs and satisfy the core requirements of power electronic systems for high frequency, miniaturization, and high efficiency. Among them, the double-trench 4H-SiC MOSFET (DT-MOS) developed by ROHM has been widely adopted in power electronic systems such as three-phase inverters for new energy vehicles and wind power generation. Nevertheless, the conventional DT-MOS (CON-DTMOS) suffers from prominent performance limitations. Restricted by the wide-bandgap characteristics of 4H-SiC materials, its parasitic body diode exhibits poor reverse freewheeling capability and high conduction loss, accompanied by severe bipolar degradation. In addition, the drawbacks of CON-DTMOS, including large on-resistance, high gate-drain capacitance, and excessive reverse recovery charge, further limit its application scope. To address the aforementioned performance deficiencies of CON-DTMOS, this paper proposes two novel device structures, namely LV-DTMOS and RC-ASMOS. By introducing planar channels and reverse channels, the proposed structures reduce the on-resistance and reverse turn-on voltage and effectively suppress the bipolar degradation induced by the body diode. Meanwhile, the optimized trench structure shields the gate-drain capacitance and improves the dynamic characteristics of the device. Consequently, the optimized 4H-SiC MOSFET with comprehensive and balanced performance is realized, which completely eliminates the bipolar degradation effect and lays a solid foundation for the reliable application of 4H-SiC MOSFETs in high-frequency power electronic scenarios. Methods This paper carries out device structure design and parameter optimization based on the Sentaurus TCAD simulation platform. Taking the conventional double-trench 4H-SiC MOSFET (CON-DTMOS) as the research baseline, a novel LV-DTMOS structure with integrated Lateral-Vertical channels is firstly designed. On this basis, an asymmetric stepped RC-ASMOS with embedded reverse channels is further proposed through structural optimization.The forward channels CH1 and CH2 can significantly reduce the on-resistance and improve the chip integration level. Moreover, the CH2 integrated at the trench bottom can shield the gate-drain coupling capacitance, thereby enhancing the dynamic performance of the device. Meanwhile, the embedded reverse channel CH3 can be turned on at a low reverse turn-on voltage through an ultra-thin oxide layer prior to the intrinsic body diode. This avoids the electron-hole recombination process and fundamentally eliminates the bipolar degradation effect.To improve the accuracy and reliability of simulation results, multiple critical physical models are adopted in the simulation process, including the incomplete ionization model, bandgap narrowing model, avalanche effect model, and high-field mobility saturation model. Furthermore, an interface charge model is introduced to account for the influence of interface state charges at the SiC/SiO₂ interface on channel mobility. The comprehensive application of the above multi-physical models enables the establishment of a simulation model that is highly consistent with the physical behaviors of practical devices, which provides a reliable support for subsequent device characteristic analysis and parameter optimization. Results and Discussions Simulation results indicate that the RC-ASMOS achieves optimal comprehensive performance under the structural and doping parameters of a CSL layer doping concentration of 4.5×10¹⁷ cm^–3, a reverse channel width of 0.35 μm, a source oxide thickness of 0.012 μm, and a P-body doping concentration of 2.0×10¹⁹ cm^–3. Compared with the conventional CON-DTMOS, the optimized RC-ASMOS exhibits substantial improvements in overall performance. The specific on-resistance of the RC-ASMOS is reduced by 29.1%, and the forward voltage drop is decreased from 2.8 V to 1.6 V, corresponding to a reduction of 42.9%. In addition, the proposed device effectively optimizes the internal electric field distribution and alleviates the electric field crowding effect, leading to a 36.5% enhancement in breakdown voltage (Fig. 11, Fig. 12). Benefiting from the CH2 integrated at the trench bottom, the gate-drain coupling effect is effectively weakened, which significantly reduces the gate-drain capacitance and lowers the gate charge by 53.9% (Fig. 13, Fig. 14. Furthermore, the RC-ASMOS realizes unipolar reverse freewheeling through the embedded reverse channel CH3, which suppresses the minority carrier storage effect and greatly improves the reverse recovery characteristics. The reverse recovery charge is reduced by 46.2%, and the peak reverse current is remarkably decreased (Fig. 15). Consequently, the proposed RC-ASMOS possesses excellent static conduction performance and high-frequency dynamic switching performance simultaneously. Conclusions Based on the conventional double-trench 4H-SiC MOSFET (CON-DTMOS), this paper conducts device design, parameter optimization, and performance verification using the Sentaurus TCAD simulation platform. Firstly, an LV-DTMOS structure with integrated planar-vertical channels is simulated. On this basis, structural optimization is further performed, and a novel RC-ASMOS device with embedded reverse channels is proposed. By optimizing the internal carrier transport paths, the RC-ASMOS achieves significant improvements in both static and dynamic device performance.Thanks to the unique reverse channel, the RC-ASMOS can be turned on for reverse freewheeling prior to the parasitic body diode, which avoids the internal electron-hole recombination process and fundamentally eliminates the bipolar degradation effect. Meanwhile, the RC-ASMOS remarkably reduces the gate-drain overlapping area, yielding a substantial improvement in dynamic characteristics. Overall, the proposed RC-ASMOS realizes comprehensive performance optimization and effectively breaks through the performance limitations of traditional 4H-SiC MOSFETs.
- Metal-Oxide-Semiconductor Field-Effect Transistor,
- Body diode,
- Source-Connected Gate,
- Reverse freewheeling,
- Bipolar degradation

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References(23)

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