Cross-Scale Functional Safety Verification: Expert-Guided Graph Learning for System-on-Chips

BIAN Yanhao; SUN Yutao; FEI Siyang; WANG Zhijun

doi:10.11999/JEIT260719

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BIAN Yanhao, SUN Yutao, FEI Siyang, WANG Zhijun. Cross-Scale Functional Safety Verification: Expert-Guided Graph Learning for System-on-Chips[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260719

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BIAN Yanhao, SUN Yutao, FEI Siyang, WANG Zhijun. Cross-Scale Functional Safety Verification: Expert-Guided Graph Learning for System-on-Chips[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260719

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Cross-Scale Functional Safety Verification: Expert-Guided Graph Learning for System-on-Chips

doi: 10.11999/JEIT260719 cstr: 32379.14.JEIT260719

School of Integrated Circuits, Beijing University of Posts and Telecommunications, Beijing 100876, China

Received Date: 2026-06-01
Accepted Date: 2026-09-15
Rev Recd Date: 2026-08-27

Available Online: 2026-09-24

Abstract

Abstract

Objective Functional safety has become a critical requirement in automotive System-on-Chip (SoC) design in compliance with the ISO 26262 functional safety standard. Conventional exhaustive fault injection faces prohibitive computational costs in large-scale circuits, which may result in insufficient identification of critical fault regions or overly conservative protection strategies. Existing learning-based methods still suffer from limited cross-scale transferability, insufficient integration of circuit-domain knowledge, and inadequate support for downstream hardening decisions. This work aims to develop an accurate, efficient, and transferable framework for node-level fault-criticality prediction and low-overhead selective hardening to support automotive SoC functional safety verification. Methods A primitive-level fault dataset is constructed from 40 DesignWare (DW) library circuits covering four functional families: arithmetic and logic, communication and encoding, storage and control, and error correction and detection. Each circuit is converted into a unified directed graph with structural, connectivity, timing, and activity-related features. Node-level fault-criticality labels are generated through controlled stuck-at fault injection with ASIL-aware threshold calibration. An expert-guided graph learning model is proposed, which adopts a Graph Attention Network (GAT) with residual connections to learn transferable fault-sensitive representations. A four-layer expert rule calibration module is further developed to incorporate circuit-domain knowledge. The propagation-oriented rules emphasize nodes with strong fault propagation capability, such as high fan-out and critical-path nodes; the safety-context rules enhance the evaluation of clock-domain crossings and reset-related logic; the confidence-correction rules reduce unstable predictions and false positives; and the circuit-adaptive rules dynamically adjust rule intensity according to different functional families. Furthermore, an explanation-based node ranking mechanism combining structural and feature attribution analyses is established to form a prediction-explanation-hardening closed-loop framework for targeted protection (Fig. 1, Fig. 2). Results and Discussions The proposed method is evaluated on nine benchmark circuits with gate counts ranging from 273 to 15 290. The results show that the method achieves an accuracy of up to 99.4% and outperforms GAT, CNN, and three state-of-the-art methods on all test circuits (Fig. 3, Table 4). The introduction of expert rules increases the average accuracy and F1 score by 1.77 and 1.98 percentage points, respectively, with greater improvements observed in complex circuits (Fig. 7, Fig. 8). Ablation experiments demonstrate that the four functional families provide complementary fault knowledge and jointly enhance cross-scale generalization capability (Fig. 5, Fig. 6). Compared with traditional fault simulation, the proposed framework achieves a geometric mean speedup of 166.4× and a maximum speedup of 1 119× on I2C, while the explainability module introduces only approximately 20% additional computational overhead (Fig. 9). The selective hardening strategy reduces area overhead by 8.35%～14.95% compared with global Triple Modular Redundancy (TMR), while maintaining the Single-Point Fault Metric (SPFM) above 99.3% and the Latent Fault Metric (LFM) above 89.0%. All nine circuits achieve the SPFM target value associated with ASIL-D, eight circuits satisfy both SPFM and LFM target values associated with ASIL-D, and the remaining circuit satisfies the corresponding ASIL-C target values (Fig. 10, Fig. 11). Conclusions The proposed framework enables effective cross-scale fault-criticality prediction by learning transferable fault-sensitive patterns from primitive circuits without retraining on target designs. It achieves high prediction accuracy, substantial acceleration, and low hardware overhead while satisfying ISO 26262-related functional safety requirements. Future work will expand primitive dataset coverage, incorporate causal inference to reduce dependence on manually designed expert rules, and explore extensions toward heterogeneous chiplet architectures.
- Functional safety,
- Automotive System-on-Chip (SoC),
- Fault injection,
- Graph Neural Networks (GNN),
- Selective hardening

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References(28)

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